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(parent: 1aa3d08) | patch
fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave
authorDave Liu <daveliu@freescale.com>
Wed, 16 Dec 2009 16:24:39 +0000 (10:24 -0600)
committerKumar Gala <galak@kernel.crashing.org>
Tue, 5 Jan 2010 19:50:07 +0000 (13:50 -0600)
commit3e731aaba30c7011edf6391072eee845ed1b816f
treeff32b3e1f2bbec7abfcd740f4dda254bd92cf0abtree | snapshot
parent1aa3d08a0244506b94031522e54fe06ee7a5ae0ecommit | diff
fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave

In chip-select interleaving case, we also need set the ODT_RD_CFG
and ODT_WR_CFG in cs1_config register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
cpu/mpc8xxx/ddr/ctrl_regs.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git