git.sur5r.net Git - u-boot/commit

]> git.sur5r.net Git - u-boot/commit

author	York Sun <yorksun@freescale.com>
	Mon, 8 Sep 2014 19:20:00 +0000 (12:20 -0700)
committer	York Sun <yorksun@freescale.com>
	Thu, 25 Sep 2014 15:36:19 +0000 (08:36 -0700)
commit	40f8dec54d7803975aed1c88327002c95ea99908
tree	83f7778c9179e518631ce308f3504a1e6e634c57	tree \| snapshot
parent	f43b4356a794be647011132f4f2dc970a29a9dd5	commit \| diff

armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot Page

Secondary cores need to be released from holdoff by boot release
registers. With GPP bootrom, they can boot from main memory
directly. Individual spin table is used for each core. Spin table
and the boot page is reserved in device tree so OS won't overwrite.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>

12 files changed:

arch/arm/cpu/armv8/fsl-lsch3/Makefile		diff \| blob \| history
arch/arm/cpu/armv8/fsl-lsch3/cpu.c		diff \| blob \| history
arch/arm/cpu/armv8/fsl-lsch3/cpu.h		diff \| blob \| history
arch/arm/cpu/armv8/fsl-lsch3/fdt.c	[new file with mode: 0644]	blob
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S		diff \| blob \| history
arch/arm/cpu/armv8/fsl-lsch3/mp.c	[new file with mode: 0644]	blob
arch/arm/cpu/armv8/fsl-lsch3/mp.h	[new file with mode: 0644]	blob
arch/arm/cpu/armv8/transition.S		diff \| blob \| history
arch/arm/include/asm/arch-fsl-lsch3/config.h		diff \| blob \| history
arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h		diff \| blob \| history
arch/arm/include/asm/macro.h		diff \| blob \| history
arch/arm/lib/gic_64.S		diff \| blob \| history

Cloned from git://git.denx.de/u-boot.git

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