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(parent: 23a12cb) | patch
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs
authorRajesh Bhagat <rajesh.bhagat@nxp.com>
Wed, 17 Jan 2018 10:43:06 +0000 (16:13 +0530)
committerYork Sun <york.sun@nxp.com>
Tue, 23 Jan 2018 19:20:03 +0000 (11:20 -0800)
commit554d33f3db3cdbb02f440ab3b667ff2bc3cfa2b1
tree32f7d0ba67574dbb9c660935008e0abcf9743f7btree | snapshot
parent23a12cb3d05ee2caa860bee7b6f0ebcb40afaccecommit | diff
ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs

Sets DDR configuration parameter cdr1 before all other settings
to support case 0.9v VDD is enabled for some SoCs

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
drivers/ddr/fsl/fsl_ddr_gen4.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git