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(parent: 1cf6cac) | patch
clk: zynq: Show watchdog clock rate properly
authorMichal Simek <michal.simek@xilinx.com>
Wed, 21 Feb 2018 14:06:20 +0000 (15:06 +0100)
committerMichal Simek <michal.simek@xilinx.com>
Fri, 23 Mar 2018 08:34:43 +0000 (09:34 +0100)
commit58afff43e3a8f31344cbbc6a3f09bd3f7a2a70eb
treef455d56690cba8e4c9062d55c7b8dce40888d29atree | snapshot
parent1cf6cac4d16ef5e9f7c0fa9cd62275924626a130commit | diff
clk: zynq: Show watchdog clock rate properly

watchdog clock is also connected to cpu 1X clocksource.

Zynq> clk dump
...

Before:
      swdt          4294967290
After:
      swdt           111111110

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
drivers/clk/clk_zynq.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git