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(parent: 73175d0) | patch
arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch
authorLey Foon Tan <ley.foon.tan@intel.com>
Fri, 18 May 2018 14:05:25 +0000 (22:05 +0800)
committerMarek Vasut <marex@denx.de>
Fri, 18 May 2018 08:30:48 +0000 (10:30 +0200)
commit5fb033a3368d78cc1d2460cc4db5880398513b26
tree0038d41b489c1f31ece1464f6dad29b0aeafa77ctree | snapshot
parent73175d04a9351857e4314cbe4cd64cbb9f27c69ecommit | diff
arm: socfpga: misc: Add CONFIG_SYS_L2_PL310 switch

Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is
accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch
conditional build in order this file can by shared across other SOCFPGAs.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
arch/arm/mach-socfpga/misc.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git