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(parent: b375d84) | patch
rockchip: clk: Add rk3368 SARADC clock support
authorDavid Wu <david.wu@rock-chips.com>
Wed, 20 Sep 2017 06:37:50 +0000 (14:37 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Sat, 30 Sep 2017 22:33:30 +0000 (00:33 +0200)
commit615514c16dee4d43bd584ea326a5a56ebcb89c85
treec9a66b0378ef68ef7f9273b4598d0143cb7d5a1ctree | snapshot
parentb375d84135e26d5ec5034a515af4df5981785f37commit | diff
rockchip: clk: Add rk3368 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 8-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
arch/arm/include/asm/arch-rockchip/cru_rk3368.h diff | blob | history
drivers/clk/rockchip/clk_rk3368.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git