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(parent: 81ca840) | patch
imx: mx6q DDR3 init: Fix tMRD
authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Wed, 30 Jan 2013 11:19:13 +0000 (11:19 +0000)
committerStefano Babic <sbabic@denx.de>
Tue, 12 Feb 2013 12:52:30 +0000 (13:52 +0100)
commit6904e377465db6c731adf4fb0eb67e55454606d7
tree7dbec95763d0392f007717f316f20241774addf7tree | snapshot
parent81ca840976e8e418ae8decaf03ea01f59b1b5be2commit | diff
imx: mx6q DDR3 init: Fix tMRD

MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.

For all DDR3 speed bins:
  tMRD(min) = 4 nCK
  tMOD(min) = max(12 nCK, 15 ns)

Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Tested-by: Eric Nelson <eric.nelson@boundarydevices.com>
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff | blob | history
Cloned from git://git.denx.de/u-boot.git