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(parent: 915e098) | patch
rockchip: clk: rk3036: correct setting for pll integer mode
authorKever Yang <kever.yang@rock-chips.com>
Tue, 13 Jun 2017 02:03:11 +0000 (10:03 +0800)
committerPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fri, 23 Jun 2017 14:40:23 +0000 (16:40 +0200)
commit6a464d9cab63f5317bc914e2de52a4de98377743
treedeba93cf20a02a60c6a703b260d874eb3cc8f5cftree | snapshot
parent915e09814a83128fee8b87b2ee2e5f4a17e04a01commit | diff
rockchip: clk: rk3036: correct setting for pll integer mode

According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
integer mode, while the '0' means the frac mode.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
drivers/clk/rockchip/clk_rk3036.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git