]> git.sur5r.net Git - u-boot/commit
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling
authorSRICHARAN R <r.sricharan@ti.com>
Fri, 8 Nov 2013 12:10:37 +0000 (17:40 +0530)
committerTom Rini <trini@ti.com>
Wed, 4 Dec 2013 13:12:08 +0000 (08:12 -0500)
commit6c70935d7525a4b2b144b49457d2bae85f1d111a
tree663b91f30c048968bcef5a4bf3916b123c51f7ab
parent39302dcd3013134e936cc76ccee8d1ed5522bfa0
ARM: DRA: EMIF: Change DDR3 settings to use hw leveling

Currently the DDR3 memory on DRA7 ES1.0 evm board is enabled using
software leveling. This was done since hardware leveling was not
working. Now that the right sequence to do hw leveling is identified,
use it. This is required for EMIF clockdomain to idle and come back
during lowpower usecases.

Signed-off-by: Sricharan R <r.sricharan@ti.com>
arch/arm/cpu/armv7/omap-common/emif-common.c
arch/arm/cpu/armv7/omap5/hw_data.c
arch/arm/cpu/armv7/omap5/hwinit.c
arch/arm/cpu/armv7/omap5/sdram.c
arch/arm/include/asm/arch-omap5/omap.h
arch/arm/include/asm/emif.h