]> git.sur5r.net Git - u-boot/commit
OMAP3 Move cache routine to cache.S
authorTom Rix <Tom.Rix@windriver.com>
Thu, 10 Sep 2009 19:27:57 +0000 (15:27 -0400)
committerTom Rix <Tom.Rix@windriver.com>
Tue, 13 Oct 2009 11:17:33 +0000 (06:17 -0500)
commit7a2aa8b68120f333ed2edc33475ca195810d6cb1
tree90d5ca33c5e1464bda6f439e4b1f04d164b78d16
parenta16df2c11188297eca43cf6080c70fb69b960232
OMAP3 Move cache routine to cache.S

v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp r0, #0
   beq earlier_than_label

Which was lost information to

   cmp r0, #CPU_3XX_ES20
   blt earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
cpu/arm_cortexa8/cpu.c
cpu/arm_cortexa8/omap3/Makefile
cpu/arm_cortexa8/omap3/board.c
cpu/arm_cortexa8/omap3/cache.S [new file with mode: 0644]
cpu/arm_cortexa8/omap3/cache.c [deleted file]
cpu/arm_cortexa8/start.S
include/asm-arm/arch-omap3/omap3.h
include/asm-arm/arch-omap3/sys_proto.h