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omap5/dra7: i2c: correct register offset for sync register
authorMugunthan V N <mugunthanvnm@ti.com>
Mon, 18 Jul 2016 09:40:57 +0000 (15:10 +0530)
committerHeiko Schocher <hs@denx.de>
Tue, 26 Jul 2016 06:39:23 +0000 (08:39 +0200)
commit7fb825f5b112713f572917fa7e89aac2b5b9c7b4
treec5f7b67227ac5d60d15e31ae42469ee93c093f5ctree | snapshot
parent3465f807d4b90378d86b3904ce2db196462ddd4ecommit | diff
omap5/dra7: i2c: correct register offset for sync register

The register offset of i2c_sysc offset is not correct as per
omap5[1]/dra7[2] TRM, correct the offsets as per the
documentation.

[1] - http://www.ti.com/lit/pdf/swpu249
[2] - http://www.ti.com/lit/pdf/spruhz6

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
arch/arm/include/asm/arch-omap5/i2c.h diff | blob | history
Cloned from git://git.denx.de/u-boot.git