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driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots
authorYork Sun <yorksun@freescale.com>
Fri, 7 Nov 2014 20:14:36 +0000 (12:14 -0800)
committerYork Sun <yorksun@freescale.com>
Fri, 5 Dec 2014 16:06:11 +0000 (08:06 -0800)
commit84baed2a2bdde3b2bf876d36cc966bd41ac67a6d
tree933eef7757ee30f9d68dd933c0d6d40965fb7e41tree | snapshot
parent9a7eeb9c9fe17d39a68e8775f9cf0a1c1b81b810commit | diff
driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git