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(parent: 473af36) | patch
driver/ddr/fsl: Fix timing_cfg_2
authorYork Sun <york.sun@nxp.com>
Fri, 29 Jul 2016 16:02:29 +0000 (09:02 -0700)
committerYork Sun <york.sun@nxp.com>
Tue, 2 Aug 2016 16:47:34 +0000 (09:47 -0700)
commit8936691ba69bc322201c62e977e2803cfe67fc40
tree2c7aa873b2e5068cfc3aeefd2022719dc0e06ffftree | snapshot
parent473af36a889d3a7e6faad1ec95b926a21c834bf8commit | diff
driver/ddr/fsl: Fix timing_cfg_2

Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.

Signed-off-by: York Sun <york.sun@nxp.com>
Reported-by: Thomas Schaefer <Thomas.Schaefer@kontron.com>
drivers/ddr/fsl/ctrl_regs.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git