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(parent: adca187) | patch
imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset
authorYe.Li <B37916@freescale.com>
Tue, 9 Sep 2014 02:17:00 +0000 (10:17 +0800)
committerStefano Babic <sbabic@denx.de>
Mon, 29 Sep 2014 08:24:07 +0000 (10:24 +0200)
commit9293d7fd502ce29302fadb8b4ccb9231ec0bcc66
treefd8ef54e242e4c0a0607f86045a2e6c893a4728atree | snapshot
parentadca1875c8090dea9b163550d8607ccba5418819commit | diff
imx: mx6: Checking PLL2 PFD0 and PFD2 for periph_clk before PFD reset

Checking the pre_periph_clk_sel and pre_periph2_clk of CCM CBCMR
register, if the PLL2 PFD0 or PLL2 PFD2 is used for the clock source,
do not reset this PFD to avoid system hang. Customers may set this
in DDR script or use BT_FREQ to select low freq boot.

Signed-off-by: Ye.Li <B37916@freescale.com>
arch/arm/cpu/armv7/mx6/soc.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git