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(parent: ffd06e0) | patch
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform
authorYork Sun <yorksun@freescale.com>
Mon, 8 Oct 2012 07:44:31 +0000 (07:44 +0000)
committerAndy Fleming <afleming@freescale.com>
Mon, 22 Oct 2012 19:31:33 +0000 (14:31 -0500)
commit98ffa19053f2d10578a227de4e441698226fde0a
tree36010ca075f6ce2e62902c4b6321eff04f8cd5b4tree | snapshot
parentffd06e0231ac3fd0c5810f39f6e23527948df1c7commit | diff
powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform

New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
arch/powerpc/cpu/mpc85xx/cpu.c diff | blob | history
arch/powerpc/cpu/mpc85xx/speed.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git