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(parent: a93feb2) | patch
clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value
authorPatrice Chotard <patrice.chotard@st.com>
Fri, 19 Jan 2018 17:02:40 +0000 (18:02 +0100)
committerTom Rini <trini@konsulko.com>
Sun, 28 Jan 2018 14:39:15 +0000 (09:39 -0500)
commit990dba649852d79a3ac5f9540a713f6207cf7ea8
treefd36d56ba6c9e344287fa52d73134b8c6842d83ctree | snapshot
parenta93feb2edc60b9db76ec794bff5ad0fcb10ce3ebcommit | diff
clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
  00: PLLSAIP = 2
  01: PLLSAIP = 4
  10: PLLSAIP = 6
  11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
drivers/clk/clk_stm32f.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git