]> git.sur5r.net Git - u-boot/commit
Revert "sf: Fix quad bit set for micron devices"
authorCyrille Pitchen <cyrille.pitchen@atmel.com>
Thu, 15 Dec 2016 16:45:39 +0000 (17:45 +0100)
committerJagan Teki <jagan@openedev.com>
Thu, 15 Dec 2016 17:33:16 +0000 (18:33 +0100)
commit9bcb0188708594f7f2d86ddff3ec1fc8c1364e0d
tree8b4c0c6d6faf9b6c6fb03ad93d04f6bd97d30fcb
parentdb9225ba2686d6b7e249d00e1803bd07f71d6070
Revert "sf: Fix quad bit set for micron devices"

This reverts commit c56ae7519f141523ba1248b22b5b5169b21772fe.

Once the 'Quad Enable' bit is cleared in their Enhanced Volatile
Configuration Register (EVCR), Micron memories expect ALL commands to use
the SPI 4-4-4 protocol. Commands using SPI 1-y-z protocols are no longer
accepted.

Within the reverted commit, the write_evcr() function is implemented using
the spi_flash_write_common(), which is a shortcut for the
[ spi_flash_cmd_write_enable(), spi_flash_cmd_write(),
spi_flash_cmd_wait_ready() ] sequence.

Since the internal state of the Micron memory has been changed when the
spi_flash_cmd_write() function completes, the later call of the
spi_flash_cmd_wait_ready() function fails.

Indeed the SPI controller driver is not aware of the SPI protocol switch.

Further patches will fix the support of Micron QSPI memories.

Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
[Rebase on master, use JEDEC_MFR(info) in place of idcode0]
Signed-off-by: Jagan Teki <jagan@openedev.com>
drivers/mtd/spi/sf_internal.h
drivers/mtd/spi/spi_flash.c