]> git.sur5r.net Git - u-boot/commit
arm: socfpga: set the mpuclk divider in the Altera group register
authorDinh Nguyen <dinguyen@kernel.org>
Tue, 31 Jan 2017 18:33:08 +0000 (12:33 -0600)
committerMarek Vasut <marex@denx.de>
Wed, 8 Feb 2017 01:19:11 +0000 (02:19 +0100)
commita45526aaa0ae241f3e1df996fed988a014eeffe8
tree7963f647342de91f3fd97aaf6c5cd16ab2916e2e
parentc83a824e62277162ad35f52879b2316902c0eff5
arm: socfpga: set the mpuclk divider in the Altera group register

The mpuclk register in the Altera group of the clock manager
divides the mpu_clk that is generated from the C0 output of the main
pll.

Without this patch, the default value of the register is 1, so the mpuclk
will always get divided by 2 if the correct value is not set. For example,
on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be
1.05 GHz.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm/mach-socfpga/clock_manager.c
arch/arm/mach-socfpga/include/mach/clock_manager.h
arch/arm/mach-socfpga/wrap_pll_config.c