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(parent: bd91508) | patch
arc/cache: Flush & invalidate all caches right before enabling IOC
authorAlexey Brodkin <abrodkin@synopsys.com>
Wed, 8 Jun 2016 05:04:03 +0000 (08:04 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Mon, 13 Jun 2016 12:38:05 +0000 (14:38 +0200)
commita4a43fcf9cca1ebd3d26f9a01b923b7393d69c54
tree0195cdd23b61125ac21e0bdbb3fbeaea75794da3tree | snapshot
parentbd91508b50ade5c73b3749bf4e5ede31d2da7ef8commit | diff
arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arch/arc/lib/cache.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git