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(parent: 146251f) | patch
x86: dts: Add SPI flash MRC details for chromebook_link
authorSimon Glass <sjg@chromium.org>
Tue, 20 Jan 2015 05:16:13 +0000 (22:16 -0700)
committerSimon Glass <sjg@chromium.org>
Sat, 24 Jan 2015 13:13:45 +0000 (06:13 -0700)
commita9aff2f46a7f7d29a662531dbc181773f16a606d
tree4c340ea0b74ccb57fae8987f13b1aae994ef77b3tree | snapshot
parent146251f87eaebbd77ca9596391890b44cbda47fbcommit | diff
x86: dts: Add SPI flash MRC details for chromebook_link

Correct the SPI flash compatible string, add an alias and specify the
position of the MRC cache, used to store SDRAM training settings for the
Memory Reference Code.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/x86/dts/chromebook_link.dts diff | blob | history
Cloned from git://git.denx.de/u-boot.git