]> git.sur5r.net Git - u-boot/commit
projects / u-boot / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5380335) | patch
armv8: ls2085a: Add workaround of errata A009635
authorPrabhakar Kushwaha <prabhakar@freescale.com>
Thu, 5 Nov 2015 06:30:14 +0000 (12:00 +0530)
committerYork Sun <yorksun@freescale.com>
Mon, 30 Nov 2015 17:11:12 +0000 (09:11 -0800)
commitb4017364630fbc526bbf5e917d8fae6013805488
treeea2df6ef79c7526db3f91e1cfb06803b3e96aebdtree | snapshot
parent5380335e66e7d731bd417f0fe6fcee68750b0245commit | diff
armv8: ls2085a: Add workaround of errata A009635

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 diff | blob | history
arch/arm/cpu/armv8/fsl-layerscape/cpu.c diff | blob | history
arch/arm/cpu/armv8/fsl-layerscape/soc.c diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/config.h diff | blob | history
arch/arm/include/asm/arch-fsl-layerscape/soc.h diff | blob | history
Cloned from git://git.denx.de/u-boot.git