]> git.sur5r.net Git - u-boot/commit
spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
authorVignesh R <vigneshr@ti.com>
Wed, 21 Dec 2016 05:12:33 +0000 (10:42 +0530)
committerJagan Teki <jagan@openedev.com>
Wed, 4 Jan 2017 15:38:35 +0000 (16:38 +0100)
commitb63b46313ed29e9b0c36b3d6b9407f6eade40c8f
tree5a0e72111f7e00eff2d8dc612223d22603467499
parent57897c13de03ac0136d64641a3eab526c6810387
spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible

According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
drivers/spi/cadence_qspi_apb.c