]> git.sur5r.net Git - u-boot/commit
ppc/85xx: 32bit DDR changes for P1020/P1011
authorPoonam Aggrwal <poonam.aggrwal@freescale.com>
Sat, 19 Sep 2009 12:20:17 +0000 (17:50 +0530)
committerTom Rix <Tom.Rix@windriver.com>
Sat, 3 Oct 2009 14:04:35 +0000 (09:04 -0500)
commitbdc810a771289a94e1dc959ff2cf0074d7f42f11
tree1c76dd656ee8e30d7b9ce856eb5c97c81cc6bda4
parent36e71c07566aa9e7ecec71f52c379c7071a84d7a
ppc/85xx: 32bit DDR changes for P1020/P1011

The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.

As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
board/freescale/p1_p2_rdb/ddr.c