ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai

ppc4xx: Fix chip select timing for SysACE access on AMCC Katmai

Previous versions used full wait states for the chip select #1 which
is connected to the Xilinix SystemACE controller on the AMCC Katmai
evaluation board. This leads to really slow access and therefore low
performance. This patch now sets up the chip select a lot faster
resulting in much better read/write performance of the Linux driver.

Signed-off-by: Stefan Roese <sr@denx.de>