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(parent: 1d96cfe) | patch
ppc4xx: Reorganize DDR2 ECC handling
authorFelix Radensky <felix@embedded-sol.com>
Sun, 27 Sep 2009 21:56:12 +0000 (23:56 +0200)
committerStefan Roese <sr@denx.de>
Fri, 2 Oct 2009 11:53:28 +0000 (13:53 +0200)
commitd24bd2517a2b847f773453eab0ee5b1c8ebc74ba
treef5e7c0f371867fc03adafc3da8fe2916b245e468tree | snapshot
parent1d96cfe8f5eebfc6ea39d1a387f35ca4499e6b67commit | diff
ppc4xx: Reorganize DDR2 ECC handling

Reorganize DDR2 ECC handling to use common code for
SPD DIMMs and soldered SDRAM. Also, use common code
to display SDRAM info (ECC, CAS latency) for SPD and
soldered SDRAM variants.

Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
cpu/ppc4xx/44x_spd_ddr2.c diff | blob | history
include/ppc405.h diff | blob | history
Cloned from git://git.denx.de/u-boot.git