]> git.sur5r.net Git - u-boot/commit
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation
authormaxims@google.com <maxims@google.com>
Mon, 30 Jan 2017 19:35:04 +0000 (11:35 -0800)
committerTom Rini <trini@konsulko.com>
Wed, 8 Feb 2017 20:56:30 +0000 (15:56 -0500)
commitd5ce3574619d6814ea095a798702e342d45203d4
tree29505cad383e11e624d7fa6c94350344d29f3307
parente163a931af34ba06d11b98707b69b8819e353257
aspeed: ast2500: Fix H-PLL and M-PLL clock rate calculation

Fix H-PLL and M-PLL rate calculation in ast2500 clock driver.
Without this fix, valid setting can lead to division by zero
when requesting the rate of H-PLL or M-PLL clocks.

Signed-off-by: Maxim Sloyko <maxims@google.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
drivers/clk/aspeed/clk_ast2500.c