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(parent: 2651a05) | patch
ARM: non-sec: flush code cacheline aligned
authorStefan Agner <stefan.agner@toradex.com>
Wed, 3 Aug 2016 20:08:55 +0000 (13:08 -0700)
committerTom Rini <trini@konsulko.com>
Fri, 12 Aug 2016 13:22:15 +0000 (09:22 -0400)
commitda91cfed54ec44d88f93af2adfbdeada8ab4403e
tree0f33c7db11beb3a000cf119a7b8905b2597fbec0tree | snapshot
parent2651a052d8ab13a8609c51053ba0f693f1be3295commit | diff
ARM: non-sec: flush code cacheline aligned

Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
arch/arm/cpu/armv7/virt-v7.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git