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arc: cache - utilize IO coherency (AKA IOC) engine
authorAlexey Brodkin <Alexey.Brodkin@synopsys.com>
Mon, 14 Dec 2015 14:15:13 +0000 (17:15 +0300)
committerAlexey Brodkin <abrodkin@synopsys.com>
Sat, 20 Feb 2016 08:20:05 +0000 (11:20 +0300)
commitdb6ce2312dcae87619136457d1f9df56789f630a
tree1e894ccb3d9070f09d95a2930ea8dc3a67798ad3tree | snapshot
parent379b3280b30c4aad5ff0fdf1cd6431c5fa6861b1commit | diff
arc: cache - utilize IO coherency (AKA IOC) engine

With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.

With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
arch/arc/include/asm/arcregs.h diff | blob | history
arch/arc/lib/cache.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git