git.sur5r.net Git - u-boot/commit

]> git.sur5r.net Git - u-boot/commit

author	Priyanka Jain <priyanka.jain@nxp.com>
	Thu, 27 Apr 2017 09:38:06 +0000 (15:08 +0530)
committer	York Sun <york.sun@nxp.com>
	Tue, 23 May 2017 16:40:23 +0000 (09:40 -0700)
commit	e809e747996b00acd0ffc833999e97a3a21ddfac
tree	e62a9b5249c07df67dba198d2bdf6943a93fae14	tree \| snapshot
parent	89a168f776cbc15a2ff1f25a0f4e54f9bbaffdec	commit \| diff

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Cloned from git://git.denx.de/u-boot.git

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arch/arm/cpu/armv8/fsl-layerscape/cpu.c		diff \| blob \| history
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc		diff \| blob \| history
arch/arm/include/asm/arch-fsl-layerscape/cpu.h		diff \| blob \| history
arch/arm/include/asm/arch-fsl-layerscape/soc.h		diff \| blob \| history
drivers/pci/pcie_layerscape.c		diff \| blob \| history
drivers/pci/pcie_layerscape.h		diff \| blob \| history
drivers/pci/pcie_layerscape_fixup.c		diff \| blob \| history