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(parent: d5555b7) | patch
net: macb: Flush correct cache portion when sending
authorSimon Glass <sjg@chromium.org>
Thu, 5 May 2016 13:28:10 +0000 (07:28 -0600)
committerAndreas Bießmann <andreas@biessmann.org>
Sun, 12 Jun 2016 21:49:38 +0000 (23:49 +0200)
commitf589f8cca64bddb59fe2409c10ab14529ab47a40
treed04d7ee3227dda189c3e930e6c782d1fc9f091f7tree | snapshot
parentd5555b70e6cdbce4e1395f40c19a504015f93668commit | diff
net: macb: Flush correct cache portion when sending

The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
drivers/net/macb.c diff | blob | history
Cloned from git://git.denx.de/u-boot.git