]> git.sur5r.net Git - freertos/commit
Re-org of RISC-V file structure and naming step 2.
authorrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 30 Dec 2018 23:53:47 +0000 (23:53 +0000)
committerrtel <rtel@1d2547de-c912-0410-9cb9-b8ca96c0e9e2>
Sun, 30 Dec 2018 23:53:47 +0000 (23:53 +0000)
commitf7fa3e0bc24519d2605efe81d16ece1fbeb5e286
tree3037d894090dcb479f7c9ec166e7c177dd99f497
parent8ac2c5cb01b2c5eb89d49528dcc4aefbbcb71d03
Re-org of RISC-V file structure and naming step 2.

git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2620 1d2547de-c912-0410-9cb9-b8ca96c0e9e2
FreeRTOS/Demo/RISC-V-Qemu-sifive_e-FreedomStudio/.cproject
FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/.cproject
FreeRTOS/Demo/RISC-V_Renode_Emulator_SoftConsole/Microsemi_Code/riscv_hal/entry.S
FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h [new file with mode: 0644]
FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_port_specific_extensions.h [deleted file]
FreeRTOS/Source/portable/GCC/RISC-V-RV32/chip_specific_extensions/readme.txt [new file with mode: 0644]
FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_chip_specific_extensions.h [new file with mode: 0644]
FreeRTOS/Source/portable/GCC/RISC-V-RV32/freertos_risc_v_port_specific_extensions.h [deleted file]
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
FreeRTOS/Source/portable/GCC/RISC-V-RV32/readme.txt