-#define UDMA_CHCTL_DSTINC_M 0xC0000000 /* Destination Address Increment */\r
-#define UDMA_CHCTL_DSTINC_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_DSTINC_16 0x40000000 /* Half-word */\r
-#define UDMA_CHCTL_DSTINC_32 0x80000000 /* Word */\r
-#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 /* No increment */\r
-#define UDMA_CHCTL_DSTSIZE_M 0x30000000 /* Destination Data Size */\r
-#define UDMA_CHCTL_DSTSIZE_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_DSTSIZE_16 0x10000000 /* Half-word */\r
-#define UDMA_CHCTL_DSTSIZE_32 0x20000000 /* Word */\r
-#define UDMA_CHCTL_SRCINC_M 0x0C000000 /* Source Address Increment */\r
-#define UDMA_CHCTL_SRCINC_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_SRCINC_16 0x04000000 /* Half-word */\r
-#define UDMA_CHCTL_SRCINC_32 0x08000000 /* Word */\r
-#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 /* No increment */\r
-#define UDMA_CHCTL_SRCSIZE_M 0x03000000 /* Source Data Size */\r
-#define UDMA_CHCTL_SRCSIZE_8 0x00000000 /* Byte */\r
-#define UDMA_CHCTL_SRCSIZE_16 0x01000000 /* Half-word */\r
-#define UDMA_CHCTL_SRCSIZE_32 0x02000000 /* Word */\r
-#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 /* Arbitration Size */\r
-#define UDMA_CHCTL_ARBSIZE_1 0x00000000 /* 1 Transfer */\r
-#define UDMA_CHCTL_ARBSIZE_2 0x00004000 /* 2 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_4 0x00008000 /* 4 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 /* 8 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_16 0x00010000 /* 16 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_32 0x00014000 /* 32 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_64 0x00018000 /* 64 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 /* 128 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_256 0x00020000 /* 256 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_512 0x00024000 /* 512 Transfers */\r
-#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 /* 1024 Transfers */\r
-#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 /* Transfer Size (minus 1) */\r
-#define UDMA_CHCTL_NXTUSEBURST 0x00000008 /* Next Useburst */\r
-#define UDMA_CHCTL_XFERMODE_M 0x00000007 /* uDMA Transfer Mode */\r
-#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 /* Stop */\r
-#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 /* Basic */\r
-#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 /* Auto-Request */\r
-#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 /* Ping-Pong */\r
-#define UDMA_CHCTL_XFERMODE_MEM_SG 0x00000004 /* Memory Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_MEM_SGA 0x00000005 /* Alternate Memory Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_PER_SG 0x00000006 /* Peripheral Scatter-Gather */\r
-#define UDMA_CHCTL_XFERMODE_PER_SGA 0x00000007 /* Alternate Peripheral */\r
- /* Scatter-Gather */\r
-#define UDMA_CHCTL_XFERSIZE_S 4\r
-\r
-\r
-//*****************************************************************************\r
-// DWT Bits\r
-//*****************************************************************************\r
-/* DWT_CTRL[DWT_CTRL_CYCCNTENA] Bits */\r
-#define DWT_CTRL_CYCCNTENA_OFS ( 0) /* CYCCNTENA Offset */\r
-#define DWT_CTRL_CYCCNTENA (0x00000001) /* */\r
-/* DWT_CTRL[DWT_CTRL_POSTPRESET] Bits */\r
-#define DWT_CTRL_POSTPRESET_OFS ( 1) /* POSTPRESET Offset */\r
-#define DWT_CTRL_POSTPRESET_M (0x0000001e) /* */\r
-/* DWT_CTRL[DWT_CTRL_POSTCNT] Bits */\r
-#define DWT_CTRL_POSTCNT_OFS ( 5) /* POSTCNT Offset */\r
-#define DWT_CTRL_POSTCNT_M (0x000001e0) /* */\r
-/* DWT_CTRL[DWT_CTRL_CYCTAP] Bits */\r
-#define DWT_CTRL_CYCTAP_OFS ( 9) /* CYCTAP Offset */\r
-#define DWT_CTRL_CYCTAP (0x00000200) /* */\r
-/* DWT_CTRL[DWT_CTRL_SYNCTAP] Bits */\r
-#define DWT_CTRL_SYNCTAP_OFS (10) /* SYNCTAP Offset */\r
-#define DWT_CTRL_SYNCTAP_M (0x00000c00) /* */\r
-#define DWT_CTRL_SYNCTAP0 (0x00000400) /* */\r
-#define DWT_CTRL_SYNCTAP1 (0x00000800) /* */\r
-#define DWT_CTRL_SYNCTAP_0 (0x00000000) /* Disabled. No synch counting. */\r
-#define DWT_CTRL_SYNCTAP_1 (0x00000400) /* Tap at CYCCNT bit 24. */\r
-#define DWT_CTRL_SYNCTAP_2 (0x00000800) /* Tap at CYCCNT bit 26. */\r
-#define DWT_CTRL_SYNCTAP_3 (0x00000c00) /* Tap at CYCCNT bit 28. */\r
-/* DWT_CTRL[DWT_CTRL_PCSAMPLEENA] Bits */\r
-#define DWT_CTRL_PCSAMPLEENA_OFS (12) /* PCSAMPLEENA Offset */\r
-#define DWT_CTRL_PCSAMPLEENA (0x00001000) /* */\r
-/* DWT_CTRL[DWT_CTRL_EXCTRCENA] Bits */\r
-#define DWT_CTRL_EXCTRCENA_OFS (16) /* EXCTRCENA Offset */\r
-#define DWT_CTRL_EXCTRCENA (0x00010000) /* */\r
-/* DWT_CTRL[DWT_CTRL_CPIEVTENA] Bits */\r
-#define DWT_CTRL_CPIEVTENA_OFS (17) /* CPIEVTENA Offset */\r
-#define DWT_CTRL_CPIEVTENA (0x00020000) /* */\r
-/* DWT_CTRL[DWT_CTRL_EXCEVTENA] Bits */\r
-#define DWT_CTRL_EXCEVTENA_OFS (18) /* EXCEVTENA Offset */\r
-#define DWT_CTRL_EXCEVTENA (0x00040000) /* */\r
-/* DWT_CTRL[DWT_CTRL_SLEEPEVTENA] Bits */\r
-#define DWT_CTRL_SLEEPEVTENA_OFS (19) /* SLEEPEVTENA Offset */\r
-#define DWT_CTRL_SLEEPEVTENA (0x00080000) /* */\r
-/* DWT_CTRL[DWT_CTRL_LSUEVTENA] Bits */\r
-#define DWT_CTRL_LSUEVTENA_OFS (20) /* LSUEVTENA Offset */\r
-#define DWT_CTRL_LSUEVTENA (0x00100000) /* */\r
-/* DWT_CTRL[DWT_CTRL_FOLDEVTENA] Bits */\r
-#define DWT_CTRL_FOLDEVTENA_OFS (21) /* FOLDEVTENA Offset */\r
-#define DWT_CTRL_FOLDEVTENA (0x00200000) /* */\r
-/* DWT_CTRL[DWT_CTRL_CYCEVTENA] Bits */\r
-#define DWT_CTRL_CYCEVTENA_OFS (22) /* CYCEVTENA Offset */\r
-#define DWT_CTRL_CYCEVTENA (0x00400000) /* */\r
-/* DWT_CTRL[DWT_CTRL_NOPRFCNT] Bits */\r
-#define DWT_CTRL_NOPRFCNT_OFS (24) /* NOPRFCNT Offset */\r
-#define DWT_CTRL_NOPRFCNT (0x01000000) /* */\r
-/* DWT_CTRL[DWT_CTRL_NOCYCCNT] Bits */\r
-#define DWT_CTRL_NOCYCCNT_OFS (25) /* NOCYCCNT Offset */\r
-#define DWT_CTRL_NOCYCCNT (0x02000000) /* */\r
-/* DWT_CPICNT[DWT_CPICNT_CPICNT] Bits */\r
-#define DWT_CPICNT_CPICNT_OFS ( 0) /* CPICNT Offset */\r
-#define DWT_CPICNT_CPICNT_M (0x000000ff) /* */\r
-/* DWT_EXCCNT[DWT_EXCCNT_EXCCNT] Bits */\r
-#define DWT_EXCCNT_EXCCNT_OFS ( 0) /* EXCCNT Offset */\r
-#define DWT_EXCCNT_EXCCNT_M (0x000000ff) /* */\r
-/* DWT_SLEEPCNT[DWT_SLEEPCNT_SLEEPCNT] Bits */\r
-#define DWT_SLEEPCNT_SLEEPCNT_OFS ( 0) /* SLEEPCNT Offset */\r
-#define DWT_SLEEPCNT_SLEEPCNT_M (0x000000ff) /* */\r
-/* DWT_LSUCNT[DWT_LSUCNT_LSUCNT] Bits */\r
-#define DWT_LSUCNT_LSUCNT_OFS ( 0) /* LSUCNT Offset */\r
-#define DWT_LSUCNT_LSUCNT_M (0x000000ff) /* */\r
-/* DWT_FOLDCNT[DWT_FOLDCNT_FOLDCNT] Bits */\r
-#define DWT_FOLDCNT_FOLDCNT_OFS ( 0) /* FOLDCNT Offset */\r
-#define DWT_FOLDCNT_FOLDCNT_M (0x000000ff) /* */\r
-/* DWT_MASK0[DWT_MASK0_MASK] Bits */\r
-#define DWT_MASK0_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK0_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_FUNCTION] Bits */\r
-#define DWT_FUNCTION0_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION0_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION0_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION0_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION0_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION0_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION0_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION0_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION0_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION0_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION0_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION0_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION0_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION0_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION0_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION0_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION0_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION0_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION0_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION0_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_EMITRANGE] Bits */\r
-#define DWT_FUNCTION0_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION0_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION0_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION0_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_LNK1ENA] Bits */\r
-#define DWT_FUNCTION0_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION0_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION0_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION0_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION0_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION0_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION0_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION0_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION0_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION0_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION0_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION0_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION0[DWT_FUNCTION0_MATCHED] Bits */\r
-#define DWT_FUNCTION0_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION0_MATCHED (0x01000000) /* */\r
-/* DWT_MASK1[DWT_MASK1_MASK] Bits */\r
-#define DWT_MASK1_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK1_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_FUNCTION] Bits */\r
-#define DWT_FUNCTION1_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION1_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION1_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION1_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION1_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION1_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION1_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION1_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION1_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION1_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION1_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION1_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION1_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION1_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION1_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION1_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION1_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION1_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION1_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION1_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_EMITRANGE] Bits */\r
-#define DWT_FUNCTION1_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION1_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_CYCMATCH] Bits */\r
-#define DWT_FUNCTION1_CYCMATCH_OFS ( 7) /* CYCMATCH Offset */\r
-#define DWT_FUNCTION1_CYCMATCH (0x00000080) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION1_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION1_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_LNK1ENA] Bits */\r
-#define DWT_FUNCTION1_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION1_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION1_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION1_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION1_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION1_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION1_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION1_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION1_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION1_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION1_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION1_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION1[DWT_FUNCTION1_MATCHED] Bits */\r
-#define DWT_FUNCTION1_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION1_MATCHED (0x01000000) /* */\r
-/* DWT_MASK2[DWT_MASK2_MASK] Bits */\r
-#define DWT_MASK2_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK2_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_FUNCTION] Bits */\r
-#define DWT_FUNCTION2_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION2_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION2_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION2_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION2_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION2_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION2_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION2_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION2_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION2_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION2_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION2_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION2_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION2_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION2_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION2_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION2_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION2_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION2_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION2_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_EMITRANGE] Bits */\r
-#define DWT_FUNCTION2_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION2_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION2_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION2_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_LNK1ENA] Bits */\r
-#define DWT_FUNCTION2_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION2_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION2_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION2_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION2_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION2_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION2_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION2_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION2_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION2_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION2_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION2_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION2[DWT_FUNCTION2_MATCHED] Bits */\r
-#define DWT_FUNCTION2_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION2_MATCHED (0x01000000) /* */\r
-/* DWT_MASK3[DWT_MASK3_MASK] Bits */\r
-#define DWT_MASK3_MASK_OFS ( 0) /* MASK Offset */\r
-#define DWT_MASK3_MASK_M (0x0000000f) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_FUNCTION] Bits */\r
-#define DWT_FUNCTION3_FUNCTION_OFS ( 0) /* FUNCTION Offset */\r
-#define DWT_FUNCTION3_FUNCTION_M (0x0000000f) /* */\r
-#define DWT_FUNCTION3_FUNCTION0 (0x00000001) /* */\r
-#define DWT_FUNCTION3_FUNCTION1 (0x00000002) /* */\r
-#define DWT_FUNCTION3_FUNCTION2 (0x00000004) /* */\r
-#define DWT_FUNCTION3_FUNCTION3 (0x00000008) /* */\r
-#define DWT_FUNCTION3_FUNCTION_0 (0x00000000) /* Disabled */\r
-#define DWT_FUNCTION3_FUNCTION_1 (0x00000001) /* EMITRANGE = 0, sample and emit PC through ITM. EMITRANGE = 1, emit address offset through ITM */\r
-#define DWT_FUNCTION3_FUNCTION_2 (0x00000002) /* EMITRANGE = 0, emit data through ITM on read and write. EMITRANGE = 1, emit data and address offset through ITM on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_3 (0x00000003) /* EMITRANGE = 0, sample PC and data value through ITM on read or write. EMITRANGE = 1, emit address offset and data value through ITM on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_4 (0x00000004) /* Watchpoint on PC match. */\r
-#define DWT_FUNCTION3_FUNCTION_5 (0x00000005) /* Watchpoint on read. */\r
-#define DWT_FUNCTION3_FUNCTION_6 (0x00000006) /* Watchpoint on write. */\r
-#define DWT_FUNCTION3_FUNCTION_7 (0x00000007) /* Watchpoint on read or write. */\r
-#define DWT_FUNCTION3_FUNCTION_8 (0x00000008) /* ETM trigger on PC match */\r
-#define DWT_FUNCTION3_FUNCTION_9 (0x00000009) /* ETM trigger on read */\r
-#define DWT_FUNCTION3_FUNCTION_10 (0x0000000a) /* ETM trigger on write */\r
-#define DWT_FUNCTION3_FUNCTION_11 (0x0000000b) /* ETM trigger on read or write */\r
-#define DWT_FUNCTION3_FUNCTION_12 (0x0000000c) /* EMITRANGE = 0, sample data for read transfers. EMITRANGE = 1, sample Daddr [15:0] for read transfers */\r
-#define DWT_FUNCTION3_FUNCTION_13 (0x0000000d) /* EMITRANGE = 0, sample data for write transfers. EMITRANGE = 1, sample Daddr [15:0] for write transfers */\r
-#define DWT_FUNCTION3_FUNCTION_14 (0x0000000e) /* EMITRANGE = 0, sample PC + data for read transfers. EMITRANGE = 1, sample Daddr [15:0] + data for read transfers */\r
-#define DWT_FUNCTION3_FUNCTION_15 (0x0000000f) /* EMITRANGE = 0, sample PC + data for write transfers. EMITRANGE = 1, sample Daddr [15:0] + data for write transfers */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_EMITRANGE] Bits */\r
-#define DWT_FUNCTION3_EMITRANGE_OFS ( 5) /* EMITRANGE Offset */\r
-#define DWT_FUNCTION3_EMITRANGE (0x00000020) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVMATCH] Bits */\r
-#define DWT_FUNCTION3_DATAVMATCH_OFS ( 8) /* DATAVMATCH Offset */\r
-#define DWT_FUNCTION3_DATAVMATCH (0x00000100) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_LNK1ENA] Bits */\r
-#define DWT_FUNCTION3_LNK1ENA_OFS ( 9) /* LNK1ENA Offset */\r
-#define DWT_FUNCTION3_LNK1ENA (0x00000200) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVSIZE] Bits */\r
-#define DWT_FUNCTION3_DATAVSIZE_OFS (10) /* DATAVSIZE Offset */\r
-#define DWT_FUNCTION3_DATAVSIZE_M (0x00000c00) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE0 (0x00000400) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE1 (0x00000800) /* */\r
-#define DWT_FUNCTION3_DATAVSIZE_0 (0x00000000) /* byte */\r
-#define DWT_FUNCTION3_DATAVSIZE_1 (0x00000400) /* halfword */\r
-#define DWT_FUNCTION3_DATAVSIZE_2 (0x00000800) /* word */\r
-#define DWT_FUNCTION3_DATAVSIZE_3 (0x00000c00) /* Unpredictable. */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR0] Bits */\r
-#define DWT_FUNCTION3_DATAVADDR0_OFS (12) /* DATAVADDR0 Offset */\r
-#define DWT_FUNCTION3_DATAVADDR0_M (0x0000f000) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_DATAVADDR1] Bits */\r
-#define DWT_FUNCTION3_DATAVADDR1_OFS (16) /* DATAVADDR1 Offset */\r
-#define DWT_FUNCTION3_DATAVADDR1_M (0x000f0000) /* */\r
-/* DWT_FUNCTION3[DWT_FUNCTION3_MATCHED] Bits */\r
-#define DWT_FUNCTION3_MATCHED_OFS (24) /* MATCHED Offset */\r
-#define DWT_FUNCTION3_MATCHED (0x01000000) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A0 Bits\r
-//*****************************************************************************\r
-/* UCA0CTLW0[UCSWRST] Bits */\r
-#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA0CTLW0[UCTXBRK] Bits */\r
-#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA0CTLW0[UCTXADDR] Bits */\r
-#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA0CTLW0[UCDORM] Bits */\r
-#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-#define UCDORM (0x0008) /* Dormant */\r
-/* UCA0CTLW0[UCBRKIE] Bits */\r
-#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA0CTLW0[UCRXEIE] Bits */\r
-#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA0CTLW0[UCSSEL] Bits */\r
-#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-#define UCSSEL_0 (0x0000) /* UCLK */\r
-#define UCSSEL_1 (0x0040) /* ACLK */\r
-#define UCSSEL_2 (0x0080) /* SMCLK */\r
-#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA0CTLW0[UCSYNC] Bits */\r
-#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA0CTLW0[UCMODE] Bits */\r
-#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-#define UCMODE_0 (0x0000) /* UART mode */\r
-#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA0CTLW0[UCSPB] Bits */\r
-#define UCSPB_OFS (11) /* UCSPB Offset */\r
-#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA0CTLW0[UC7BIT] Bits */\r
-#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-#define UC7BIT (0x1000) /* Character length */\r
-/* UCA0CTLW0[UCMSB] Bits */\r
-#define UCMSB_OFS (13) /* UCMSB Offset */\r
-#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA0CTLW0[UCPAR] Bits */\r
-#define UCPAR_OFS (14) /* UCPAR Offset */\r
-#define UCPAR (0x4000) /* Parity select */\r
-/* UCA0CTLW0[UCPEN] Bits */\r
-#define UCPEN_OFS (15) /* UCPEN Offset */\r
-#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA0CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA0CTLW0_SPI[UCSTEM] Bits */\r
-#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA0CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA0CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA0CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA0CTLW0_SPI[UCMST] Bits */\r
-#define UCMST_OFS (11) /* UCMST Offset */\r
-#define UCMST (0x0800) /* Master mode select */\r
-/* UCA0CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA0CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA0CTLW0_SPI[UCCKPL] Bits */\r
-#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA0CTLW0_SPI[UCCKPH] Bits */\r
-#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA0CTLW1[UCGLIT] Bits */\r
-#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-#define UCGLIT_M (0x0003) /* Deglitch time */\r
-#define UCGLIT0 (0x0001) /* Deglitch time */\r
-#define UCGLIT1 (0x0002) /* Deglitch time */\r
-#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA0MCTLW[UCOS16] Bits */\r
-#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA0MCTLW[UCBRF] Bits */\r
-#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA0MCTLW[UCBRS] Bits */\r
-#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA0STATW[UCBUSY] Bits */\r
-#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA0STATW[UCADDR_UCIDLE] Bits */\r
-#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA0STATW[UCRXERR] Bits */\r
-#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA0STATW[UCBRK] Bits */\r
-#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA0STATW[UCPE] Bits */\r
-#define UCPE_OFS ( 4) /* UCPE Offset */\r
-#define UCPE (0x0010) /* */\r
-/* UCA0STATW[UCOE] Bits */\r
-#define UCOE_OFS ( 5) /* UCOE Offset */\r
-#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA0STATW[UCFE] Bits */\r
-#define UCFE_OFS ( 6) /* UCFE Offset */\r
-#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA0STATW[UCLISTEN] Bits */\r
-#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA0STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA0STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA0STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA0STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA0RXBUF[UCRXBUF] Bits */\r
-#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA0RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA0TXBUF[UCTXBUF] Bits */\r
-#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA0TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA0ABCTL[UCABDEN] Bits */\r
-#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA0ABCTL[UCBTOE] Bits */\r
-#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA0ABCTL[UCSTOE] Bits */\r
-#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA0ABCTL[UCDELIM] Bits */\r
-#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA0IRCTL[UCIREN] Bits */\r
-#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA0IRCTL[UCIRTXCLK] Bits */\r
-#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA0IRCTL[UCIRTXPL] Bits */\r
-#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA0IRCTL[UCIRRXFE] Bits */\r
-#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA0IRCTL[UCIRRXPL] Bits */\r
-#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA0IRCTL[UCIRRXFL] Bits */\r
-#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA0IE[UCRXIE] Bits */\r
-#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA0IE[UCTXIE] Bits */\r
-#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA0IE[UCSTTIE] Bits */\r
-#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA0IE[UCTXCPTIE] Bits */\r
-#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA0IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA0IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA0IFG[UCRXIFG] Bits */\r
-#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA0IFG[UCTXIFG] Bits */\r
-#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA0IFG[UCSTTIFG] Bits */\r
-#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA0IFG[UCTXCPTIFG] Bits */\r
-#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA0IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA0IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A1 Bits\r
-//*****************************************************************************\r
-/* UCA1CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA1CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA1CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA1CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA1CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA1CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA1CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA1CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA1CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA1CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA1CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA1CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA1CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA1CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA1CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA1CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA1CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA1CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA1CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA1CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA1CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA1CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA1CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA1CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA1CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA1MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA1MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA1MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA1STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA1STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA1STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA1STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA1STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA1STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA1STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA1STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA1STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA1STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA1STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA1STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA1RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA1RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA1TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA1TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA1ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA1ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA1ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA1ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA1IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA1IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA1IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA1IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA1IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA1IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA1IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA1IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA1IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA1IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA1IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA1IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA1IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA1IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA1IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA1IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA1IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA1IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A2 Bits\r
-//*****************************************************************************\r
-/* UCA2CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA2CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA2CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA2CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA2CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA2CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA2CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA2CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA2CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA2CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA2CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA2CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA2CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA2CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA2CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA2CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA2CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA2CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA2CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA2CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA2CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA2CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA2CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA2CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA2CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA2MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA2MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA2MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA2STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA2STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA2STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA2STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA2STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA2STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA2STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA2STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA2STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA2STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA2STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA2STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA2RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA2RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA2TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA2TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA2ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA2ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA2ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA2ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA2IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA2IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA2IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA2IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA2IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA2IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA2IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA2IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA2IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA2IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA2IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA2IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA2IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA2IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA2IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA2IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA2IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA2IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_A3 Bits\r
-//*****************************************************************************\r
-/* UCA3CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA3CTLW0[UCTXBRK] Bits */\r
-//#define UCTXBRK_OFS ( 1) /* UCTXBRK Offset */\r
-//#define UCTXBRK (0x0002) /* Transmit break */\r
-/* UCA3CTLW0[UCTXADDR] Bits */\r
-//#define UCTXADDR_OFS ( 2) /* UCTXADDR Offset */\r
-//#define UCTXADDR (0x0004) /* Transmit address */\r
-/* UCA3CTLW0[UCDORM] Bits */\r
-//#define UCDORM_OFS ( 3) /* UCDORM Offset */\r
-//#define UCDORM (0x0008) /* Dormant */\r
-/* UCA3CTLW0[UCBRKIE] Bits */\r
-//#define UCBRKIE_OFS ( 4) /* UCBRKIE Offset */\r
-//#define UCBRKIE (0x0010) /* Receive break character interrupt enable */\r
-/* UCA3CTLW0[UCRXEIE] Bits */\r
-//#define UCRXEIE_OFS ( 5) /* UCRXEIE Offset */\r
-//#define UCRXEIE (0x0020) /* Receive erroneous-character interrupt enable */\r
-/* UCA3CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLK */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLK (0x0000) /* UCLK */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA3CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA3CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_A mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_A mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_A mode */\r
-//#define UCMODE_0 (0x0000) /* UART mode */\r
-//#define UCMODE_1 (0x0200) /* Idle-line multiprocessor mode */\r
-//#define UCMODE_2 (0x0400) /* Address-bit multiprocessor mode */\r
-//#define UCMODE_3 (0x0600) /* UART mode with automatic baud-rate detection */\r
-/* UCA3CTLW0[UCSPB] Bits */\r
-//#define UCSPB_OFS (11) /* UCSPB Offset */\r
-//#define UCSPB (0x0800) /* Stop bit select */\r
-/* UCA3CTLW0[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA3CTLW0[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA3CTLW0[UCPAR] Bits */\r
-//#define UCPAR_OFS (14) /* UCPAR Offset */\r
-//#define UCPAR (0x4000) /* Parity select */\r
-/* UCA3CTLW0[UCPEN] Bits */\r
-//#define UCPEN_OFS (15) /* UCPEN Offset */\r
-//#define UCPEN (0x8000) /* Parity enable */\r
-/* UCA3CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCA3CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCA3CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_A clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_A clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_A clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-/* UCA3CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCA3CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-/* UCA3CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCA3CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCA3CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCA3CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCA3CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCA3CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* Approximately 2 ns (equivalent of 1 delay element) */\r
-//#define UCGLIT_1 (0x0001) /* Approximately 50 ns */\r
-//#define UCGLIT_2 (0x0002) /* Approximately 100 ns */\r
-//#define UCGLIT_3 (0x0003) /* Approximately 200 ns */\r
-/* UCA3MCTLW[UCOS16] Bits */\r
-//#define UCOS16_OFS ( 0) /* UCOS16 Offset */\r
-//#define UCOS16 (0x0001) /* Oversampling mode enabled */\r
-/* UCA3MCTLW[UCBRF] Bits */\r
-//#define UCBRF_OFS ( 4) /* UCBRF Offset */\r
-//#define UCBRF_M (0x00f0) /* First modulation stage select */\r
-/* UCA3MCTLW[UCBRS] Bits */\r
-//#define UCBRS_OFS ( 8) /* UCBRS Offset */\r
-//#define UCBRS_M (0xff00) /* Second modulation stage select */\r
-/* UCA3STATW[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA3STATW[UCADDR_UCIDLE] Bits */\r
-//#define UCADDR_UCIDLE_OFS ( 1) /* UCADDR_UCIDLE Offset */\r
-//#define UCADDR_UCIDLE (0x0002) /* Address received / Idle line detected */\r
-/* UCA3STATW[UCRXERR] Bits */\r
-//#define UCRXERR_OFS ( 2) /* UCRXERR Offset */\r
-//#define UCRXERR (0x0004) /* Receive error flag */\r
-/* UCA3STATW[UCBRK] Bits */\r
-//#define UCBRK_OFS ( 3) /* UCBRK Offset */\r
-//#define UCBRK (0x0008) /* Break detect flag */\r
-/* UCA3STATW[UCPE] Bits */\r
-//#define UCPE_OFS ( 4) /* UCPE Offset */\r
-//#define UCPE (0x0010) /* */\r
-/* UCA3STATW[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA3STATW[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA3STATW[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA3STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_A busy */\r
-/* UCA3STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCA3STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCA3STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCA3RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA3RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCA3TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA3TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCA3ABCTL[UCABDEN] Bits */\r
-//#define UCABDEN_OFS ( 0) /* UCABDEN Offset */\r
-//#define UCABDEN (0x0001) /* Automatic baud-rate detect enable */\r
-/* UCA3ABCTL[UCBTOE] Bits */\r
-//#define UCBTOE_OFS ( 2) /* UCBTOE Offset */\r
-//#define UCBTOE (0x0004) /* Break time out error */\r
-/* UCA3ABCTL[UCSTOE] Bits */\r
-//#define UCSTOE_OFS ( 3) /* UCSTOE Offset */\r
-//#define UCSTOE (0x0008) /* Synch field time out error */\r
-/* UCA3ABCTL[UCDELIM] Bits */\r
-//#define UCDELIM_OFS ( 4) /* UCDELIM Offset */\r
-//#define UCDELIM_M (0x0030) /* Break/synch delimiter length */\r
-//#define UCDELIM0 (0x0010) /* Break/synch delimiter length */\r
-//#define UCDELIM1 (0x0020) /* Break/synch delimiter length */\r
-//#define UCDELIM_0 (0x0000) /* 1 bit time */\r
-//#define UCDELIM_1 (0x0010) /* 2 bit times */\r
-//#define UCDELIM_2 (0x0020) /* 3 bit times */\r
-//#define UCDELIM_3 (0x0030) /* 4 bit times */\r
-/* UCA3IRCTL[UCIREN] Bits */\r
-//#define UCIREN_OFS ( 0) /* UCIREN Offset */\r
-//#define UCIREN (0x0001) /* IrDA encoder/decoder enable */\r
-/* UCA3IRCTL[UCIRTXCLK] Bits */\r
-//#define UCIRTXCLK_OFS ( 1) /* UCIRTXCLK Offset */\r
-//#define UCIRTXCLK (0x0002) /* IrDA transmit pulse clock select */\r
-/* UCA3IRCTL[UCIRTXPL] Bits */\r
-//#define UCIRTXPL_OFS ( 2) /* UCIRTXPL Offset */\r
-//#define UCIRTXPL_M (0x00fc) /* Transmit pulse length */\r
-/* UCA3IRCTL[UCIRRXFE] Bits */\r
-//#define UCIRRXFE_OFS ( 8) /* UCIRRXFE Offset */\r
-//#define UCIRRXFE (0x0100) /* IrDA receive filter enabled */\r
-/* UCA3IRCTL[UCIRRXPL] Bits */\r
-//#define UCIRRXPL_OFS ( 9) /* UCIRRXPL Offset */\r
-//#define UCIRRXPL (0x0200) /* IrDA receive input UCAxRXD polarity */\r
-/* UCA3IRCTL[UCIRRXFL] Bits */\r
-//#define UCIRRXFL_OFS (10) /* UCIRRXFL Offset */\r
-//#define UCIRRXFL_M (0x3c00) /* Receive filter length */\r
-/* UCA3IE[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA3IE[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA3IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* Start bit interrupt enable */\r
-/* UCA3IE[UCTXCPTIE] Bits */\r
-//#define UCTXCPTIE_OFS ( 3) /* UCTXCPTIE Offset */\r
-//#define UCTXCPTIE (0x0008) /* Transmit complete interrupt enable */\r
-/* UCA3IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCA3IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCA3IFG[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA3IFG[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-/* UCA3IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* Start bit interrupt flag */\r
-/* UCA3IFG[UCTXCPTIFG] Bits */\r
-//#define UCTXCPTIFG_OFS ( 3) /* UCTXCPTIFG Offset */\r
-//#define UCTXCPTIFG (0x0008) /* Transmit ready interrupt enable */\r
-/* UCA3IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCA3IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B0 Bits\r
-//*****************************************************************************\r
-/* UCB0CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB0CTLW0[UCTXSTT] Bits */\r
-#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB0CTLW0[UCTXSTP] Bits */\r
-#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB0CTLW0[UCTXNACK] Bits */\r
-#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB0CTLW0[UCTR] Bits */\r
-#define UCTR_OFS ( 4) /* UCTR Offset */\r
-#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB0CTLW0[UCTXACK] Bits */\r
-#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB0CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB0CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB0CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB0CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB0CTLW0[UCMM] Bits */\r
-#define UCMM_OFS (13) /* UCMM Offset */\r
-#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB0CTLW0[UCSLA10] Bits */\r
-#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB0CTLW0[UCA10] Bits */\r
-#define UCA10_OFS (15) /* UCA10 Offset */\r
-#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB0CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB0CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB0CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB0CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB0CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB0CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB0CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB0CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB0CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB0CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB0CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB0CTLW1[UCASTP] Bits */\r
-#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB0CTLW1[UCSWACK] Bits */\r
-#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB0CTLW1[UCSTPNACK] Bits */\r
-#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB0CTLW1[UCCLTO] Bits */\r
-#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB0CTLW1[UCETXINT] Bits */\r
-#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB0STATW[UCBBUSY] Bits */\r
-#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB0STATW[UCGC] Bits */\r
-#define UCGC_OFS ( 5) /* UCGC Offset */\r
-#define UCGC (0x0020) /* General call address received */\r
-/* UCB0STATW[UCSCLLOW] Bits */\r
-#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB0STATW[UCBCNT] Bits */\r
-#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB0STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB0STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB0STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB0STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB0TBCNT[UCTBCNT] Bits */\r
-#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB0RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB0RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB0TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB0TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB0I2COA0[I2COA0] Bits */\r
-#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA0[UCOAEN] Bits */\r
-#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA0[UCGCEN] Bits */\r
-#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB0I2COA1[I2COA1] Bits */\r
-#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA2[I2COA2] Bits */\r
-#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0I2COA3[I2COA3] Bits */\r
-#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB0I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB0ADDRX[ADDRX] Bits */\r
-#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB0ADDMASK[ADDMASK] Bits */\r
-#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-#define ADDMASK_M (0x03ff) /* */\r
-/* UCB0I2CSA[I2CSA] Bits */\r
-#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB0IE[UCRXIE0] Bits */\r
-#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB0IE[UCTXIE0] Bits */\r
-#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB0IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB0IE[UCSTPIE] Bits */\r
-#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB0IE[UCALIE] Bits */\r
-#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB0IE[UCNACKIE] Bits */\r
-#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB0IE[UCBCNTIE] Bits */\r
-#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB0IE[UCCLTOIE] Bits */\r
-#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB0IE[UCRXIE1] Bits */\r
-#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB0IE[UCTXIE1] Bits */\r
-#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB0IE[UCRXIE2] Bits */\r
-#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB0IE[UCTXIE2] Bits */\r
-#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB0IE[UCRXIE3] Bits */\r
-#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB0IE[UCTXIE3] Bits */\r
-#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB0IE[UCBIT9IE] Bits */\r
-#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB0IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB0IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB0IFG[UCRXIFG0] Bits */\r
-#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB0IFG[UCTXIFG0] Bits */\r
-#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB0IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB0IFG[UCSTPIFG] Bits */\r
-#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB0IFG[UCALIFG] Bits */\r
-#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB0IFG[UCNACKIFG] Bits */\r
-#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB0IFG[UCBCNTIFG] Bits */\r
-#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB0IFG[UCCLTOIFG] Bits */\r
-#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB0IFG[UCRXIFG1] Bits */\r
-#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB0IFG[UCTXIFG1] Bits */\r
-#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB0IFG[UCRXIFG2] Bits */\r
-#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB0IFG[UCTXIFG2] Bits */\r
-#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB0IFG[UCRXIFG3] Bits */\r
-#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB0IFG[UCTXIFG3] Bits */\r
-#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB0IFG[UCBIT9IFG] Bits */\r
-#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB0IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB0IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B1 Bits\r
-//*****************************************************************************\r
-/* UCB1CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB1CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB1CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB1CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB1CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB1CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB1CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB1CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB1CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB1CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB1CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB1CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB1CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB1CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB1CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB1CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB1CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB1CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB1CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB1CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB1CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB1CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB1CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB1CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB1CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB1CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB1CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB1CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB1CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB1STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB1STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB1STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB1STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB1STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB1STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB1STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB1STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB1TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB1RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB1RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB1TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB1TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB1I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB1I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB1I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB1ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB1ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB1I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB1IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB1IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB1IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB1IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB1IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB1IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB1IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB1IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB1IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB1IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB1IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB1IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB1IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB1IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB1IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB1IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB1IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB1IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB1IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB1IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB1IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB1IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB1IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB1IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB1IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB1IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB1IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB1IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB1IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB1IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB1IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB1IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB1IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB1IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B2 Bits\r
-//*****************************************************************************\r
-/* UCB2CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB2CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB2CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB2CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB2CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB2CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB2CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB2CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB2CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB2CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB2CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB2CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB2CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB2CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB2CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB2CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB2CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB2CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB2CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB2CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB2CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB2CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB2CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB2CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB2CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB2CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB2CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB2CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB2CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB2STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB2STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB2STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB2STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB2STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB2STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB2STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB2STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB2TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB2RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB2RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB2TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB2TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB2I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB2I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB2I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB2ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB2ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB2I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB2IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB2IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB2IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB2IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB2IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB2IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB2IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB2IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB2IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB2IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB2IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB2IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB2IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB2IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB2IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB2IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB2IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB2IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB2IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB2IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB2IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB2IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB2IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB2IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB2IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB2IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB2IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB2IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB2IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB2IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB2IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB2IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB2IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB2IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// EUSCI_B3 Bits\r
-//*****************************************************************************\r
-/* UCB3CTLW0[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB3CTLW0[UCTXSTT] Bits */\r
-//#define UCTXSTT_OFS ( 1) /* UCTXSTT Offset */\r
-//#define UCTXSTT (0x0002) /* Transmit START condition in master mode */\r
-/* UCB3CTLW0[UCTXSTP] Bits */\r
-//#define UCTXSTP_OFS ( 2) /* UCTXSTP Offset */\r
-//#define UCTXSTP (0x0004) /* Transmit STOP condition in master mode */\r
-/* UCB3CTLW0[UCTXNACK] Bits */\r
-//#define UCTXNACK_OFS ( 3) /* UCTXNACK Offset */\r
-//#define UCTXNACK (0x0008) /* Transmit a NACK */\r
-/* UCB3CTLW0[UCTR] Bits */\r
-//#define UCTR_OFS ( 4) /* UCTR Offset */\r
-//#define UCTR (0x0010) /* Transmitter/receiver */\r
-/* UCB3CTLW0[UCTXACK] Bits */\r
-//#define UCTXACK_OFS ( 5) /* UCTXACK Offset */\r
-//#define UCTXACK (0x0020) /* Transmit ACK condition in slave mode */\r
-/* UCB3CTLW0[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_0 (0x0000) /* UCLKI */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL__UCLKI (0x0000) /* UCLKI */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB3CTLW0[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB3CTLW0[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI_B mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI_B mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI_B mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI (master or slave enabled if STE = 1) */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI (master or slave enabled if STE = 0) */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB3CTLW0[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB3CTLW0[UCMM] Bits */\r
-//#define UCMM_OFS (13) /* UCMM Offset */\r
-//#define UCMM (0x2000) /* Multi-master environment select */\r
-/* UCB3CTLW0[UCSLA10] Bits */\r
-//#define UCSLA10_OFS (14) /* UCSLA10 Offset */\r
-//#define UCSLA10 (0x4000) /* Slave addressing mode select */\r
-/* UCB3CTLW0[UCA10] Bits */\r
-//#define UCA10_OFS (15) /* UCA10 Offset */\r
-//#define UCA10 (0x8000) /* Own addressing mode select */\r
-/* UCB3CTLW0_SPI[UCSWRST] Bits */\r
-//#define UCSWRST_OFS ( 0) /* UCSWRST Offset */\r
-//#define UCSWRST (0x0001) /* Software reset enable */\r
-/* UCB3CTLW0_SPI[UCSTEM] Bits */\r
-//#define UCSTEM_OFS ( 1) /* UCSTEM Offset */\r
-//#define UCSTEM (0x0002) /* STE mode select in master mode. */\r
-/* UCB3CTLW0_SPI[UCSSEL] Bits */\r
-//#define UCSSEL_OFS ( 6) /* UCSSEL Offset */\r
-//#define UCSSEL_M (0x00c0) /* eUSCI_B clock source select */\r
-//#define UCSSEL0 (0x0040) /* eUSCI_B clock source select */\r
-//#define UCSSEL1 (0x0080) /* eUSCI_B clock source select */\r
-//#define UCSSEL_1 (0x0040) /* ACLK */\r
-//#define UCSSEL_2 (0x0080) /* SMCLK */\r
-//#define UCSSEL_0 (0x0000) /* Reserved */\r
-//#define UCSSEL__ACLK (0x0040) /* ACLK */\r
-//#define UCSSEL__SMCLK (0x0080) /* SMCLK */\r
-//#define UCSSEL_3 (0x00c0) /* SMCLK */\r
-/* UCB3CTLW0_SPI[UCSYNC] Bits */\r
-//#define UCSYNC_OFS ( 8) /* UCSYNC Offset */\r
-//#define UCSYNC (0x0100) /* Synchronous mode enable */\r
-/* UCB3CTLW0_SPI[UCMODE] Bits */\r
-//#define UCMODE_OFS ( 9) /* UCMODE Offset */\r
-//#define UCMODE_M (0x0600) /* eUSCI mode */\r
-//#define UCMODE0 (0x0200) /* eUSCI mode */\r
-//#define UCMODE1 (0x0400) /* eUSCI mode */\r
-//#define UCMODE_0 (0x0000) /* 3-pin SPI */\r
-//#define UCMODE_1 (0x0200) /* 4-pin SPI with UCxSTE active high: Slave enabled when UCxSTE = 1 */\r
-//#define UCMODE_2 (0x0400) /* 4-pin SPI with UCxSTE active low: Slave enabled when UCxSTE = 0 */\r
-//#define UCMODE_3 (0x0600) /* I2C mode */\r
-/* UCB3CTLW0_SPI[UCMST] Bits */\r
-//#define UCMST_OFS (11) /* UCMST Offset */\r
-//#define UCMST (0x0800) /* Master mode select */\r
-/* UCB3CTLW0_SPI[UC7BIT] Bits */\r
-//#define UC7BIT_OFS (12) /* UC7BIT Offset */\r
-//#define UC7BIT (0x1000) /* Character length */\r
-/* UCB3CTLW0_SPI[UCMSB] Bits */\r
-//#define UCMSB_OFS (13) /* UCMSB Offset */\r
-//#define UCMSB (0x2000) /* MSB first select */\r
-/* UCB3CTLW0_SPI[UCCKPL] Bits */\r
-//#define UCCKPL_OFS (14) /* UCCKPL Offset */\r
-//#define UCCKPL (0x4000) /* Clock polarity select */\r
-/* UCB3CTLW0_SPI[UCCKPH] Bits */\r
-//#define UCCKPH_OFS (15) /* UCCKPH Offset */\r
-//#define UCCKPH (0x8000) /* Clock phase select */\r
-/* UCB3CTLW1[UCGLIT] Bits */\r
-//#define UCGLIT_OFS ( 0) /* UCGLIT Offset */\r
-//#define UCGLIT_M (0x0003) /* Deglitch time */\r
-//#define UCGLIT0 (0x0001) /* Deglitch time */\r
-//#define UCGLIT1 (0x0002) /* Deglitch time */\r
-//#define UCGLIT_0 (0x0000) /* 50 ns */\r
-//#define UCGLIT_1 (0x0001) /* 25 ns */\r
-//#define UCGLIT_2 (0x0002) /* 12.5 ns */\r
-//#define UCGLIT_3 (0x0003) /* 6.25 ns */\r
-/* UCB3CTLW1[UCASTP] Bits */\r
-//#define UCASTP_OFS ( 2) /* UCASTP Offset */\r
-//#define UCASTP_M (0x000c) /* Automatic STOP condition generation */\r
-//#define UCASTP0 (0x0004) /* Automatic STOP condition generation */\r
-//#define UCASTP1 (0x0008) /* Automatic STOP condition generation */\r
-//#define UCASTP_0 (0x0000) /* No automatic STOP generation. The STOP condition is generated after the user sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
-//#define UCASTP_1 (0x0004) /* UCBCNTIFG is set with the byte counter reaches the threshold defined in UCBxTBCNT */\r
-//#define UCASTP_2 (0x0008) /* A STOP condition is generated automatically after the byte counter value reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the threshold */\r
-/* UCB3CTLW1[UCSWACK] Bits */\r
-//#define UCSWACK_OFS ( 4) /* UCSWACK Offset */\r
-//#define UCSWACK (0x0010) /* SW or HW ACK control */\r
-/* UCB3CTLW1[UCSTPNACK] Bits */\r
-//#define UCSTPNACK_OFS ( 5) /* UCSTPNACK Offset */\r
-//#define UCSTPNACK (0x0020) /* ACK all master bytes */\r
-/* UCB3CTLW1[UCCLTO] Bits */\r
-//#define UCCLTO_OFS ( 6) /* UCCLTO Offset */\r
-//#define UCCLTO_M (0x00c0) /* Clock low timeout select */\r
-//#define UCCLTO0 (0x0040) /* Clock low timeout select */\r
-//#define UCCLTO1 (0x0080) /* Clock low timeout select */\r
-//#define UCCLTO_0 (0x0000) /* Disable clock low timeout counter */\r
-//#define UCCLTO_1 (0x0040) /* 135 000 SYSCLK cycles (approximately 28 ms) */\r
-//#define UCCLTO_2 (0x0080) /* 150 000 SYSCLK cycles (approximately 31 ms) */\r
-//#define UCCLTO_3 (0x00c0) /* 165 000 SYSCLK cycles (approximately 34 ms) */\r
-/* UCB3CTLW1[UCETXINT] Bits */\r
-//#define UCETXINT_OFS ( 8) /* UCETXINT Offset */\r
-//#define UCETXINT (0x0100) /* Early UCTXIFG0 */\r
-/* UCB3STATW[UCBBUSY] Bits */\r
-//#define UCBBUSY_OFS ( 4) /* UCBBUSY Offset */\r
-//#define UCBBUSY (0x0010) /* Bus busy */\r
-/* UCB3STATW[UCGC] Bits */\r
-//#define UCGC_OFS ( 5) /* UCGC Offset */\r
-//#define UCGC (0x0020) /* General call address received */\r
-/* UCB3STATW[UCSCLLOW] Bits */\r
-//#define UCSCLLOW_OFS ( 6) /* UCSCLLOW Offset */\r
-//#define UCSCLLOW (0x0040) /* SCL low */\r
-/* UCB3STATW[UCBCNT] Bits */\r
-//#define UCBCNT_OFS ( 8) /* UCBCNT Offset */\r
-//#define UCBCNT_M (0xff00) /* Hardware byte counter value */\r
-/* UCB3STATW_SPI[UCBUSY] Bits */\r
-//#define UCBUSY_OFS ( 0) /* UCBUSY Offset */\r
-//#define UCBUSY (0x0001) /* eUSCI_B busy */\r
-/* UCB3STATW_SPI[UCOE] Bits */\r
-//#define UCOE_OFS ( 5) /* UCOE Offset */\r
-//#define UCOE (0x0020) /* Overrun error flag */\r
-/* UCB3STATW_SPI[UCFE] Bits */\r
-//#define UCFE_OFS ( 6) /* UCFE Offset */\r
-//#define UCFE (0x0040) /* Framing error flag */\r
-/* UCB3STATW_SPI[UCLISTEN] Bits */\r
-//#define UCLISTEN_OFS ( 7) /* UCLISTEN Offset */\r
-//#define UCLISTEN (0x0080) /* Listen enable */\r
-/* UCB3TBCNT[UCTBCNT] Bits */\r
-//#define UCTBCNT_OFS ( 0) /* UCTBCNT Offset */\r
-//#define UCTBCNT_M (0x00ff) /* Byte counter threshold value */\r
-/* UCB3RXBUF[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB3RXBUF_SPI[UCRXBUF] Bits */\r
-//#define UCRXBUF_OFS ( 0) /* UCRXBUF Offset */\r
-//#define UCRXBUF_M (0x00ff) /* Receive data buffer */\r
-/* UCB3TXBUF[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB3TXBUF_SPI[UCTXBUF] Bits */\r
-//#define UCTXBUF_OFS ( 0) /* UCTXBUF Offset */\r
-//#define UCTXBUF_M (0x00ff) /* Transmit data buffer */\r
-/* UCB3I2COA0[I2COA0] Bits */\r
-//#define I2COA0_OFS ( 0) /* I2COA0 Offset */\r
-//#define I2COA0_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA0[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA0[UCGCEN] Bits */\r
-//#define UCGCEN_OFS (15) /* UCGCEN Offset */\r
-//#define UCGCEN (0x8000) /* General call response enable */\r
-/* UCB3I2COA1[I2COA1] Bits */\r
-//#define I2COA1_OFS ( 0) /* I2COA1 Offset */\r
-//#define I2COA1_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA1[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA2[I2COA2] Bits */\r
-//#define I2COA2_OFS ( 0) /* I2COA2 Offset */\r
-//#define I2COA2_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA2[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3I2COA3[I2COA3] Bits */\r
-//#define I2COA3_OFS ( 0) /* I2COA3 Offset */\r
-//#define I2COA3_M (0x03ff) /* I2C own address */\r
-/* UCB3I2COA3[UCOAEN] Bits */\r
-//#define UCOAEN_OFS (10) /* UCOAEN Offset */\r
-//#define UCOAEN (0x0400) /* Own Address enable register */\r
-/* UCB3ADDRX[ADDRX] Bits */\r
-//#define ADDRX_OFS ( 0) /* ADDRX Offset */\r
-//#define ADDRX_M (0x03ff) /* Received Address Register */\r
-/* UCB3ADDMASK[ADDMASK] Bits */\r
-//#define ADDMASK_OFS ( 0) /* ADDMASK Offset */\r
-//#define ADDMASK_M (0x03ff) /* */\r
-/* UCB3I2CSA[I2CSA] Bits */\r
-//#define I2CSA_OFS ( 0) /* I2CSA Offset */\r
-//#define I2CSA_M (0x03ff) /* I2C slave address */\r
-/* UCB3IE[UCRXIE0] Bits */\r
-//#define UCRXIE0_OFS ( 0) /* UCRXIE0 Offset */\r
-//#define UCRXIE0 (0x0001) /* Receive interrupt enable 0 */\r
-/* UCB3IE[UCTXIE0] Bits */\r
-//#define UCTXIE0_OFS ( 1) /* UCTXIE0 Offset */\r
-//#define UCTXIE0 (0x0002) /* Transmit interrupt enable 0 */\r
-/* UCB3IE[UCSTTIE] Bits */\r
-//#define UCSTTIE_OFS ( 2) /* UCSTTIE Offset */\r
-//#define UCSTTIE (0x0004) /* START condition interrupt enable */\r
-/* UCB3IE[UCSTPIE] Bits */\r
-//#define UCSTPIE_OFS ( 3) /* UCSTPIE Offset */\r
-//#define UCSTPIE (0x0008) /* STOP condition interrupt enable */\r
-/* UCB3IE[UCALIE] Bits */\r
-//#define UCALIE_OFS ( 4) /* UCALIE Offset */\r
-//#define UCALIE (0x0010) /* Arbitration lost interrupt enable */\r
-/* UCB3IE[UCNACKIE] Bits */\r
-//#define UCNACKIE_OFS ( 5) /* UCNACKIE Offset */\r
-//#define UCNACKIE (0x0020) /* Not-acknowledge interrupt enable */\r
-/* UCB3IE[UCBCNTIE] Bits */\r
-//#define UCBCNTIE_OFS ( 6) /* UCBCNTIE Offset */\r
-//#define UCBCNTIE (0x0040) /* Byte counter interrupt enable */\r
-/* UCB3IE[UCCLTOIE] Bits */\r
-//#define UCCLTOIE_OFS ( 7) /* UCCLTOIE Offset */\r
-//#define UCCLTOIE (0x0080) /* Clock low timeout interrupt enable */\r
-/* UCB3IE[UCRXIE1] Bits */\r
-//#define UCRXIE1_OFS ( 8) /* UCRXIE1 Offset */\r
-//#define UCRXIE1 (0x0100) /* Receive interrupt enable 1 */\r
-/* UCB3IE[UCTXIE1] Bits */\r
-//#define UCTXIE1_OFS ( 9) /* UCTXIE1 Offset */\r
-//#define UCTXIE1 (0x0200) /* Transmit interrupt enable 1 */\r
-/* UCB3IE[UCRXIE2] Bits */\r
-//#define UCRXIE2_OFS (10) /* UCRXIE2 Offset */\r
-//#define UCRXIE2 (0x0400) /* Receive interrupt enable 2 */\r
-/* UCB3IE[UCTXIE2] Bits */\r
-//#define UCTXIE2_OFS (11) /* UCTXIE2 Offset */\r
-//#define UCTXIE2 (0x0800) /* Transmit interrupt enable 2 */\r
-/* UCB3IE[UCRXIE3] Bits */\r
-//#define UCRXIE3_OFS (12) /* UCRXIE3 Offset */\r
-//#define UCRXIE3 (0x1000) /* Receive interrupt enable 3 */\r
-/* UCB3IE[UCTXIE3] Bits */\r
-//#define UCTXIE3_OFS (13) /* UCTXIE3 Offset */\r
-//#define UCTXIE3 (0x2000) /* Transmit interrupt enable 3 */\r
-/* UCB3IE[UCBIT9IE] Bits */\r
-//#define UCBIT9IE_OFS (14) /* UCBIT9IE Offset */\r
-//#define UCBIT9IE (0x4000) /* Bit position 9 interrupt enable */\r
-/* UCB3IE_SPI[UCRXIE] Bits */\r
-//#define UCRXIE_OFS ( 0) /* UCRXIE Offset */\r
-//#define UCRXIE (0x0001) /* Receive interrupt enable */\r
-/* UCB3IE_SPI[UCTXIE] Bits */\r
-//#define UCTXIE_OFS ( 1) /* UCTXIE Offset */\r
-//#define UCTXIE (0x0002) /* Transmit interrupt enable */\r
-/* UCB3IFG[UCRXIFG0] Bits */\r
-//#define UCRXIFG0_OFS ( 0) /* UCRXIFG0 Offset */\r
-//#define UCRXIFG0 (0x0001) /* eUSCI_B receive interrupt flag 0 */\r
-/* UCB3IFG[UCTXIFG0] Bits */\r
-//#define UCTXIFG0_OFS ( 1) /* UCTXIFG0 Offset */\r
-//#define UCTXIFG0 (0x0002) /* eUSCI_B transmit interrupt flag 0 */\r
-/* UCB3IFG[UCSTTIFG] Bits */\r
-//#define UCSTTIFG_OFS ( 2) /* UCSTTIFG Offset */\r
-//#define UCSTTIFG (0x0004) /* START condition interrupt flag */\r
-/* UCB3IFG[UCSTPIFG] Bits */\r
-//#define UCSTPIFG_OFS ( 3) /* UCSTPIFG Offset */\r
-//#define UCSTPIFG (0x0008) /* STOP condition interrupt flag */\r
-/* UCB3IFG[UCALIFG] Bits */\r
-//#define UCALIFG_OFS ( 4) /* UCALIFG Offset */\r
-//#define UCALIFG (0x0010) /* Arbitration lost interrupt flag */\r
-/* UCB3IFG[UCNACKIFG] Bits */\r
-//#define UCNACKIFG_OFS ( 5) /* UCNACKIFG Offset */\r
-//#define UCNACKIFG (0x0020) /* Not-acknowledge received interrupt flag */\r
-/* UCB3IFG[UCBCNTIFG] Bits */\r
-//#define UCBCNTIFG_OFS ( 6) /* UCBCNTIFG Offset */\r
-//#define UCBCNTIFG (0x0040) /* Byte counter interrupt flag */\r
-/* UCB3IFG[UCCLTOIFG] Bits */\r
-//#define UCCLTOIFG_OFS ( 7) /* UCCLTOIFG Offset */\r
-//#define UCCLTOIFG (0x0080) /* Clock low timeout interrupt flag */\r
-/* UCB3IFG[UCRXIFG1] Bits */\r
-//#define UCRXIFG1_OFS ( 8) /* UCRXIFG1 Offset */\r
-//#define UCRXIFG1 (0x0100) /* eUSCI_B receive interrupt flag 1 */\r
-/* UCB3IFG[UCTXIFG1] Bits */\r
-//#define UCTXIFG1_OFS ( 9) /* UCTXIFG1 Offset */\r
-//#define UCTXIFG1 (0x0200) /* eUSCI_B transmit interrupt flag 1 */\r
-/* UCB3IFG[UCRXIFG2] Bits */\r
-//#define UCRXIFG2_OFS (10) /* UCRXIFG2 Offset */\r
-//#define UCRXIFG2 (0x0400) /* eUSCI_B receive interrupt flag 2 */\r
-/* UCB3IFG[UCTXIFG2] Bits */\r
-//#define UCTXIFG2_OFS (11) /* UCTXIFG2 Offset */\r
-//#define UCTXIFG2 (0x0800) /* eUSCI_B transmit interrupt flag 2 */\r
-/* UCB3IFG[UCRXIFG3] Bits */\r
-//#define UCRXIFG3_OFS (12) /* UCRXIFG3 Offset */\r
-//#define UCRXIFG3 (0x1000) /* eUSCI_B receive interrupt flag 3 */\r
-/* UCB3IFG[UCTXIFG3] Bits */\r
-//#define UCTXIFG3_OFS (13) /* UCTXIFG3 Offset */\r
-//#define UCTXIFG3 (0x2000) /* eUSCI_B transmit interrupt flag 3 */\r
-/* UCB3IFG[UCBIT9IFG] Bits */\r
-//#define UCBIT9IFG_OFS (14) /* UCBIT9IFG Offset */\r
-//#define UCBIT9IFG (0x4000) /* Bit position 9 interrupt flag */\r
-/* UCB3IFG_SPI[UCRXIFG] Bits */\r
-//#define UCRXIFG_OFS ( 0) /* UCRXIFG Offset */\r
-//#define UCRXIFG (0x0001) /* Receive interrupt flag */\r
-/* UCB3IFG_SPI[UCTXIFG] Bits */\r
-//#define UCTXIFG_OFS ( 1) /* UCTXIFG Offset */\r
-//#define UCTXIFG (0x0002) /* Transmit interrupt flag */\r
-\r
-\r
-//*****************************************************************************\r
-// FLCTL Bits\r
-//*****************************************************************************\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_PSTAT] Bits */\r
-#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /* PSTAT Offset */\r
-#define FLCTL_POWER_STAT_PSTAT_M (0x00000007) /* */\r
-#define FLCTL_POWER_STAT_PSTAT0 (0x00000001) /* */\r
-#define FLCTL_POWER_STAT_PSTAT1 (0x00000002) /* */\r
-#define FLCTL_POWER_STAT_PSTAT2 (0x00000004) /* */\r
-#define FLCTL_POWER_STAT_PSTAT_0 (0x00000000) /* Flash IP in power-down mode */\r
-#define FLCTL_POWER_STAT_PSTAT_1 (0x00000001) /* Flash IP Vdd domain power-up in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_2 (0x00000002) /* PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_3 (0x00000003) /* Flash IP SAFE_LV check in progress */\r
-#define FLCTL_POWER_STAT_PSTAT_4 (0x00000004) /* Flash IP Active */\r
-#define FLCTL_POWER_STAT_PSTAT_5 (0x00000005) /* Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */\r
-#define FLCTL_POWER_STAT_PSTAT_6 (0x00000006) /* Flash IP in Standby mode */\r
-#define FLCTL_POWER_STAT_PSTAT_7 (0x00000007) /* Flash IP in Current mirror boost state */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_LDOSTAT] Bits */\r
-#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /* LDOSTAT Offset */\r
-#define FLCTL_POWER_STAT_LDOSTAT (0x00000008) /* PSS FLDO GOOD status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_VREFSTAT] Bits */\r
-#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /* VREFSTAT Offset */\r
-#define FLCTL_POWER_STAT_VREFSTAT (0x00000010) /* PSS VREF stable status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_IREFSTAT] Bits */\r
-#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /* IREFSTAT Offset */\r
-#define FLCTL_POWER_STAT_IREFSTAT (0x00000020) /* PSS IREF stable status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_TRIMSTAT] Bits */\r
-#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /* TRIMSTAT Offset */\r
-#define FLCTL_POWER_STAT_TRIMSTAT (0x00000040) /* PSS trim done status */\r
-/* FLCTL_POWER_STAT[FLCTL_POWER_STAT_RD_2T] Bits */\r
-#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /* RD_2T Offset */\r
-#define FLCTL_POWER_STAT_RD_2T (0x00000080) /* Indicates if Flash is being accessed in 2T mode */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE] Bits */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFI] Bits */\r
-#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */\r
-#define FLCTL_BANK0_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_BUFD] Bits */\r
-#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */\r
-#define FLCTL_BANK0_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_WAIT] Bits */\r
-#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /* WAIT Offset */\r
-#define FLCTL_BANK0_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */\r
-#define FLCTL_BANK0_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */\r
-#define FLCTL_BANK0_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */\r
-/* FLCTL_BANK0_RDCTL[FLCTL_BANK0_RDCTL_RD_MODE_STATUS] Bits */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */\r
-#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE] Bits */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /* RD_MODE Offset */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_M (0x0000000f) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE0 (0x00000001) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE1 (0x00000002) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE2 (0x00000004) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE3 (0x00000008) /* Flash read mode control setting for Bank 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_1 (0x00000001) /* Read Margin 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_2 (0x00000002) /* Read Margin 1 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_3 (0x00000003) /* Program Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_4 (0x00000004) /* Erase Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_5 (0x00000005) /* Leakage Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_9 (0x00000009) /* Read Margin 0B */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_10 (0x0000000a) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFI] Bits */\r
-#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /* BUFI Offset */\r
-#define FLCTL_BANK1_RDCTL_BUFI (0x00000010) /* Enables read buffering feature for instruction fetches to this Bank */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_BUFD] Bits */\r
-#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /* BUFD Offset */\r
-#define FLCTL_BANK1_RDCTL_BUFD (0x00000020) /* Enables read buffering feature for data reads to this Bank */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_RD_MODE_STATUS] Bits */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /* RD_MODE_STATUS Offset */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_M (0x000f0000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 (0x00010000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 (0x00020000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 (0x00040000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 (0x00080000) /* Read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 (0x00000000) /* Normal read mode */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 (0x00010000) /* Read Margin 0 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 (0x00020000) /* Read Margin 1 */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 (0x00030000) /* Program Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 (0x00040000) /* Erase Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 (0x00050000) /* Leakage Verify */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 (0x00090000) /* Read Margin 0B */\r
-#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 (0x000a0000) /* Read Margin 1B */\r
-/* FLCTL_BANK1_RDCTL[FLCTL_BANK1_RDCTL_WAIT] Bits */\r
-#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /* WAIT Offset */\r
-#define FLCTL_BANK1_RDCTL_WAIT_M (0x0000f000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT0 (0x00001000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT1 (0x00002000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT2 (0x00004000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT3 (0x00008000) /* Number of wait states for read */\r
-#define FLCTL_BANK1_RDCTL_WAIT_0 (0x00000000) /* 0 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_1 (0x00001000) /* 1 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_2 (0x00002000) /* 2 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_3 (0x00003000) /* 3 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_4 (0x00004000) /* 4 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_5 (0x00005000) /* 5 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_6 (0x00006000) /* 6 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_7 (0x00007000) /* 7 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_8 (0x00008000) /* 8 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_9 (0x00009000) /* 9 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_10 (0x0000a000) /* 10 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_11 (0x0000b000) /* 11 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_12 (0x0000c000) /* 12 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_13 (0x0000d000) /* 13 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_14 (0x0000e000) /* 14 wait states */\r
-#define FLCTL_BANK1_RDCTL_WAIT_15 (0x0000f000) /* 15 wait states */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_START] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_START (0x00000001) /* Start of burst/compare operation */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_MEM_TYPE] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /* MEM_TYPE Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_M (0x00000006) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 (0x00000002) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 (0x00000004) /* Type of memory that burst is carried out on */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 (0x00000002) /* Information Memory */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 (0x00000004) /* Reserved */\r
-#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 (0x00000006) /* Engineering Memory */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_STOP_FAIL] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /* STOP_FAIL Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL (0x00000008) /* Terminate burst/compare operation */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_DATA_CMP] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /* DATA_CMP Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_DATA_CMP (0x00000010) /* Data pattern used for comparison against memory read data */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_TEST_EN] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /* TEST_EN Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_TEST_EN (0x00000040) /* Enable comparison against test data compare registers */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_BRST_STAT] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /* BRST_STAT Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_M (0x00030000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 (0x00010000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 (0x00020000) /* Status of Burst/Compare operation */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 (0x00000000) /* Idle */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 (0x00010000) /* Burst/Compare START bit written, but operation pending */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 (0x00020000) /* Burst/Compare in progress */\r
-#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 (0x00030000) /* Burst complete (status of completed burst remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CMP_ERR] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /* CMP_ERR Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_CMP_ERR (0x00040000) /* Burst/Compare Operation encountered atleast one data */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /* ADDR_ERR Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR (0x00080000) /* Burst/Compare Operation was terminated due to access to */\r
-/* FLCTL_RDBRST_CTLSTAT[FLCTL_RDBRST_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */\r
-#define FLCTL_RDBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 19-16 of this register */\r
-/* FLCTL_RDBRST_STARTADDR[FLCTL_RDBRST_STARTADDR_START_ADDRESS] Bits */\r
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */\r
-#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_M (0x001fffff) /* Start Address of Burst Operation */\r
-/* FLCTL_RDBRST_LEN[FLCTL_RDBRST_LEN_BURST_LENGTH] Bits */\r
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /* BURST_LENGTH Offset */\r
-#define FLCTL_RDBRST_LEN_BURST_LENGTH_M (0x001fffff) /* Length of Burst Operation */\r
-/* FLCTL_RDBRST_FAILADDR[FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS] Bits */\r
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /* FAIL_ADDRESS Offset */\r
-#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_M (0x001fffff) /* Reflects address of last failed compare */\r
-/* FLCTL_RDBRST_FAILCNT[FLCTL_RDBRST_FAILCNT_FAIL_COUNT] Bits */\r
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /* FAIL_COUNT Offset */\r
-#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_M (0x0001ffff) /* Number of failures encountered in burst operation */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_ENABLE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FLCTL_PRG_CTLSTAT_ENABLE (0x00000001) /* Master control for all word program operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_MODE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */\r
-#define FLCTL_PRG_CTLSTAT_MODE (0x00000002) /* Write mode */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PRE] Bits */\r
-#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /* VER_PRE Offset */\r
-#define FLCTL_PRG_CTLSTAT_VER_PRE (0x00000004) /* Controls automatic pre program verify operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_VER_PST] Bits */\r
-#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /* VER_PST Offset */\r
-#define FLCTL_PRG_CTLSTAT_VER_PST (0x00000008) /* Controls automatic post program verify operations */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_STATUS] Bits */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_M (0x00030000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS0 (0x00010000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS1 (0x00020000) /* Status of program operations in the Flash memory */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_1 (0x00010000) /* Single word program operation triggered, but pending */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_2 (0x00020000) /* Single word program in progress */\r
-#define FLCTL_PRG_CTLSTAT_STATUS_3 (0x00030000) /* Reserved (Idle) */\r
-/* FLCTL_PRG_CTLSTAT[FLCTL_PRG_CTLSTAT_BNK_ACT] Bits */\r
-#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /* BNK_ACT Offset */\r
-#define FLCTL_PRG_CTLSTAT_BNK_ACT (0x00040000) /* Bank active */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_START] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_START (0x00000001) /* Trigger start of burst program operation */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_TYPE] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /* TYPE Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_M (0x00000006) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE0 (0x00000002) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE1 (0x00000004) /* Type of memory that burst program is carried out on */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 (0x00000002) /* Information Memory */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 (0x00000004) /* Reserved */\r
-#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 (0x00000006) /* Engineering Memory */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_LEN] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /* LEN Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_M (0x00000038) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN0 (0x00000008) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN1 (0x00000010) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN2 (0x00000020) /* Length of burst */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_0 (0x00000000) /* No burst operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_1 (0x00000008) /* 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_2 (0x00000010) /* 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_3 (0x00000018) /* 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-#define FLCTL_PRGBRST_CTLSTAT_LEN_4 (0x00000020) /* 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR Register */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PRE] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /* AUTO_PRE Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE (0x00000040) /* Auto-Verify operation before the Burst Program */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_AUTO_PST] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /* AUTO_PST Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST (0x00000080) /* Auto-Verify operation after the Burst Program */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_BURST_STATUS] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /* BURST_STATUS Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_M (0x00070000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 (0x00010000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 (0x00020000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 (0x00040000) /* Status of a Burst Operation */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 (0x00000000) /* Idle (Burst not active) */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 (0x00010000) /* Burst program started but pending */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 (0x00020000) /* Burst active, with 1st 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 (0x00030000) /* Burst active, with 2nd 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 (0x00040000) /* Burst active, with 3rd 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 (0x00050000) /* Burst active, with 4th 128 bit word being written into Flash */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 (0x00060000) /* Reserved (Idle) */\r
-#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 (0x00070000) /* Burst Complete (status of completed burst remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PRE_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /* PRE_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR (0x00080000) /* Burst Operation encountered preprogram auto-verify errors */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_PST_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /* PST_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_PST_ERR (0x00100000) /* Burst Operation encountered postprogram auto-verify errors */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /* ADDR_ERR Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR (0x00200000) /* Burst Operation was terminated due to attempted program of reserved memory */\r
-/* FLCTL_PRGBRST_CTLSTAT[FLCTL_PRGBRST_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /* CLR_STAT Offset */\r
-#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT (0x00800000) /* Clear status bits 21-16 of this register */\r
-/* FLCTL_PRGBRST_STARTADDR[FLCTL_PRGBRST_STARTADDR_START_ADDRESS] Bits */\r
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /* START_ADDRESS Offset */\r
-#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_M (0x003fffff) /* Start Address of Program Burst Operation */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_START] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /* START Offset */\r
-#define FLCTL_ERASE_CTLSTAT_START (0x00000001) /* Start of Erase operation */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_MODE] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /* MODE Offset */\r
-#define FLCTL_ERASE_CTLSTAT_MODE (0x00000002) /* Erase mode selected by application */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_TYPE] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /* TYPE Offset */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_M (0x0000000c) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE0 (0x00000004) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE1 (0x00000008) /* Type of memory that erase operation is carried out on */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_0 (0x00000000) /* Main Memory */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_1 (0x00000004) /* Information Memory */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_2 (0x00000008) /* Reserved */\r
-#define FLCTL_ERASE_CTLSTAT_TYPE_3 (0x0000000c) /* Engineering Memory */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_STATUS] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /* STATUS Offset */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_M (0x00030000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS0 (0x00010000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS1 (0x00020000) /* Status of erase operations in the Flash memory */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_0 (0x00000000) /* Idle (no program operation currently active) */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_1 (0x00010000) /* Erase operation triggered to START but pending */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_2 (0x00020000) /* Erase operation in progress */\r
-#define FLCTL_ERASE_CTLSTAT_STATUS_3 (0x00030000) /* Erase operation completed (status of completed erase remains in this state unless explicitly cleared by SW) */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_ADDR_ERR] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /* ADDR_ERR Offset */\r
-#define FLCTL_ERASE_CTLSTAT_ADDR_ERR (0x00040000) /* Erase Operation was terminated due to attempted erase of reserved memory address */\r
-/* FLCTL_ERASE_CTLSTAT[FLCTL_ERASE_CTLSTAT_CLR_STAT] Bits */\r
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /* CLR_STAT Offset */\r
-#define FLCTL_ERASE_CTLSTAT_CLR_STAT (0x00080000) /* Clear status bits 18-16 of this register */\r
-/* FLCTL_ERASE_SECTADDR[FLCTL_ERASE_SECTADDR_SECT_ADDRESS] Bits */\r
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /* SECT_ADDRESS Offset */\r
-#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_M (0x003fffff) /* Address of Sector being Erased */\r
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */\r
-/* FLCTL_BANK0_INFO_WEPROT[FLCTL_BANK0_INFO_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK0_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT2] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT3] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT4] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT5] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT6] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT7] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT8] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT9] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT10] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT11] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT12] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT13] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT14] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT15] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT16] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT17] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT18] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT19] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT20] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT21] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT22] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT23] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT24] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT25] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT26] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT27] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT28] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT29] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT30] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase */\r
-/* FLCTL_BANK0_MAIN_WEPROT[FLCTL_BANK0_MAIN_WEPROT_PROT31] Bits */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */\r
-#define FLCTL_BANK0_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase */\r
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */\r
-/* FLCTL_BANK1_INFO_WEPROT[FLCTL_BANK1_INFO_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK1_INFO_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT0] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /* PROT0 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT0 (0x00000001) /* Protects Sector 0 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT1] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /* PROT1 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT1 (0x00000002) /* Protects Sector 1 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT2] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /* PROT2 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT2 (0x00000004) /* Protects Sector 2 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT3] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /* PROT3 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT3 (0x00000008) /* Protects Sector 3 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT4] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /* PROT4 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT4 (0x00000010) /* Protects Sector 4 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT5] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /* PROT5 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT5 (0x00000020) /* Protects Sector 5 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT6] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /* PROT6 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT6 (0x00000040) /* Protects Sector 6 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT7] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /* PROT7 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT7 (0x00000080) /* Protects Sector 7 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT8] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /* PROT8 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT8 (0x00000100) /* Protects Sector 8 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT9] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /* PROT9 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT9 (0x00000200) /* Protects Sector 9 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT10] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /* PROT10 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT10 (0x00000400) /* Protects Sector 10 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT11] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /* PROT11 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT11 (0x00000800) /* Protects Sector 11 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT12] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /* PROT12 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT12 (0x00001000) /* Protects Sector 12 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT13] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /* PROT13 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT13 (0x00002000) /* Protects Sector 13 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT14] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /* PROT14 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT14 (0x00004000) /* Protects Sector 14 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT15] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /* PROT15 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT15 (0x00008000) /* Protects Sector 15 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT16] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /* PROT16 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT16 (0x00010000) /* Protects Sector 16 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT17] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /* PROT17 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT17 (0x00020000) /* Protects Sector 17 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT18] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /* PROT18 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT18 (0x00040000) /* Protects Sector 18 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT19] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /* PROT19 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT19 (0x00080000) /* Protects Sector 19 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT20] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /* PROT20 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT20 (0x00100000) /* Protects Sector 20 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT21] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /* PROT21 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT21 (0x00200000) /* Protects Sector 21 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT22] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /* PROT22 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT22 (0x00400000) /* Protects Sector 22 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT23] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /* PROT23 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT23 (0x00800000) /* Protects Sector 23 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT24] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /* PROT24 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT24 (0x01000000) /* Protects Sector 24 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT25] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /* PROT25 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT25 (0x02000000) /* Protects Sector 25 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT26] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /* PROT26 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT26 (0x04000000) /* Protects Sector 26 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT27] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /* PROT27 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT27 (0x08000000) /* Protects Sector 27 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT28] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /* PROT28 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT28 (0x10000000) /* Protects Sector 28 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT29] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /* PROT29 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT29 (0x20000000) /* Protects Sector 29 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT30] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /* PROT30 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT30 (0x40000000) /* Protects Sector 30 from program or erase operations */\r
-/* FLCTL_BANK1_MAIN_WEPROT[FLCTL_BANK1_MAIN_WEPROT_PROT31] Bits */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /* PROT31 Offset */\r
-#define FLCTL_BANK1_MAIN_WEPROT_PROT31 (0x80000000) /* Protects Sector 31 from program or erase operations */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_I_BMRK] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /* I_BMRK Offset */\r
-#define FLCTL_BMRK_CTLSTAT_I_BMRK (0x00000001) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_D_BMRK] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /* D_BMRK Offset */\r
-#define FLCTL_BMRK_CTLSTAT_D_BMRK (0x00000002) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_EN] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /* CMP_EN Offset */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_EN (0x00000004) /* */\r
-/* FLCTL_BMRK_CTLSTAT[FLCTL_BMRK_CTLSTAT_CMP_SEL] Bits */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /* CMP_SEL Offset */\r
-#define FLCTL_BMRK_CTLSTAT_CMP_SEL (0x00000008) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_RDBRST] Bits */\r
-#define FLCTL_IFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_IFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_AVPRE] Bits */\r
-#define FLCTL_IFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_IFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_AVPST] Bits */\r
-#define FLCTL_IFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_IFG_AVPST (0x00000004) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRG] Bits */\r
-#define FLCTL_IFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_IFG_PRG (0x00000008) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRGB] Bits */\r
-#define FLCTL_IFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_IFG_PRGB (0x00000010) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_ERASE] Bits */\r
-#define FLCTL_IFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_IFG_ERASE (0x00000020) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_BMRK] Bits */\r
-#define FLCTL_IFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_IFG_BMRK (0x00000100) /* */\r
-/* FLCTL_IFG[FLCTL_IFG_PRG_ERR] Bits */\r
-#define FLCTL_IFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_IFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_IE[FLCTL_IE_RDBRST] Bits */\r
-#define FLCTL_IE_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_IE_RDBRST (0x00000001) /* */\r
-/* FLCTL_IE[FLCTL_IE_AVPRE] Bits */\r
-#define FLCTL_IE_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_IE_AVPRE (0x00000002) /* */\r
-/* FLCTL_IE[FLCTL_IE_AVPST] Bits */\r
-#define FLCTL_IE_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_IE_AVPST (0x00000004) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRG] Bits */\r
-#define FLCTL_IE_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_IE_PRG (0x00000008) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRGB] Bits */\r
-#define FLCTL_IE_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_IE_PRGB (0x00000010) /* */\r
-/* FLCTL_IE[FLCTL_IE_ERASE] Bits */\r
-#define FLCTL_IE_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_IE_ERASE (0x00000020) /* */\r
-/* FLCTL_IE[FLCTL_IE_BMRK] Bits */\r
-#define FLCTL_IE_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_IE_BMRK (0x00000100) /* */\r
-/* FLCTL_IE[FLCTL_IE_PRG_ERR] Bits */\r
-#define FLCTL_IE_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_IE_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_RDBRST] Bits */\r
-#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_CLRIFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPRE] Bits */\r
-#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_CLRIFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_AVPST] Bits */\r
-#define FLCTL_CLRIFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_CLRIFG_AVPST (0x00000004) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG] Bits */\r
-#define FLCTL_CLRIFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_CLRIFG_PRG (0x00000008) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRGB] Bits */\r
-#define FLCTL_CLRIFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_CLRIFG_PRGB (0x00000010) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_ERASE] Bits */\r
-#define FLCTL_CLRIFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_CLRIFG_ERASE (0x00000020) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_BMRK] Bits */\r
-#define FLCTL_CLRIFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_CLRIFG_BMRK (0x00000100) /* */\r
-/* FLCTL_CLRIFG[FLCTL_CLRIFG_PRG_ERR] Bits */\r
-#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_CLRIFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_RDBRST] Bits */\r
-#define FLCTL_SETIFG_RDBRST_OFS ( 0) /* RDBRST Offset */\r
-#define FLCTL_SETIFG_RDBRST (0x00000001) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPRE] Bits */\r
-#define FLCTL_SETIFG_AVPRE_OFS ( 1) /* AVPRE Offset */\r
-#define FLCTL_SETIFG_AVPRE (0x00000002) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_AVPST] Bits */\r
-#define FLCTL_SETIFG_AVPST_OFS ( 2) /* AVPST Offset */\r
-#define FLCTL_SETIFG_AVPST (0x00000004) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG] Bits */\r
-#define FLCTL_SETIFG_PRG_OFS ( 3) /* PRG Offset */\r
-#define FLCTL_SETIFG_PRG (0x00000008) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRGB] Bits */\r
-#define FLCTL_SETIFG_PRGB_OFS ( 4) /* PRGB Offset */\r
-#define FLCTL_SETIFG_PRGB (0x00000010) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_ERASE] Bits */\r
-#define FLCTL_SETIFG_ERASE_OFS ( 5) /* ERASE Offset */\r
-#define FLCTL_SETIFG_ERASE (0x00000020) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_BMRK] Bits */\r
-#define FLCTL_SETIFG_BMRK_OFS ( 8) /* BMRK Offset */\r
-#define FLCTL_SETIFG_BMRK (0x00000100) /* */\r
-/* FLCTL_SETIFG[FLCTL_SETIFG_PRG_ERR] Bits */\r
-#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /* PRG_ERR Offset */\r
-#define FLCTL_SETIFG_PRG_ERR (0x00000200) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP] Bits */\r
-#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_READ_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_HOLD] Bits */\r
-#define FLCTL_READ_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_READ_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_IREF_BOOST1] Bits */\r
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /* IREF_BOOST1 Offset */\r
-#define FLCTL_READ_TIMCTL_IREF_BOOST1_M (0x0000f000) /* */\r
-/* FLCTL_READ_TIMCTL[FLCTL_READ_TIMCTL_SETUP_LONG] Bits */\r
-#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /* SETUP_LONG Offset */\r
-#define FLCTL_READ_TIMCTL_SETUP_LONG_M (0x00ff0000) /* */\r
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_SETUP] Bits */\r
-#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_READMARGIN_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_READMARGIN_TIMCTL[FLCTL_READMARGIN_TIMCTL_HOLD] Bits */\r
-#define FLCTL_READMARGIN_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_READMARGIN_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_PRGVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_PRGVER_TIMCTL_ACTIVE_M (0x00000f00) /* */\r
-/* FLCTL_PRGVER_TIMCTL[FLCTL_PRGVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /* HOLD Offset */\r
-#define FLCTL_PRGVER_TIMCTL_HOLD_M (0x0000f000) /* */\r
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_ERSVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_ERSVER_TIMCTL[FLCTL_ERSVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_ERSVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_ERSVER_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_SETUP] Bits */\r
-#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_LKGVER_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_LKGVER_TIMCTL[FLCTL_LKGVER_TIMCTL_HOLD] Bits */\r
-#define FLCTL_LKGVER_TIMCTL_HOLD_OFS ( 8) /* HOLD Offset */\r
-#define FLCTL_LKGVER_TIMCTL_HOLD_M (0x00000f00) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_SETUP] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-/* FLCTL_PROGRAM_TIMCTL[FLCTL_PROGRAM_TIMCTL_HOLD] Bits */\r
-#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /* HOLD Offset */\r
-#define FLCTL_PROGRAM_TIMCTL_HOLD_M (0xf0000000) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_SETUP] Bits */\r
-#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /* SETUP Offset */\r
-#define FLCTL_ERASE_TIMCTL_SETUP_M (0x000000ff) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_ERASE_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-/* FLCTL_ERASE_TIMCTL[FLCTL_ERASE_TIMCTL_HOLD] Bits */\r
-#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /* HOLD Offset */\r
-#define FLCTL_ERASE_TIMCTL_HOLD_M (0xf0000000) /* */\r
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE] Bits */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /* BOOST_ACTIVE Offset */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_M (0x000000ff) /* */\r
-/* FLCTL_MASSERASE_TIMCTL[FLCTL_MASSERASE_TIMCTL_BOOST_HOLD] Bits */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /* BOOST_HOLD Offset */\r
-#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_M (0x0000ff00) /* */\r
-/* FLCTL_BURSTPRG_TIMCTL[FLCTL_BURSTPRG_TIMCTL_ACTIVE] Bits */\r
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /* ACTIVE Offset */\r
-#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_M (0x0fffff00) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// FPB Bits\r
-//*****************************************************************************\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_ENABLE] Bits */\r
-#define FPB_FP_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_CTRL_ENABLE (0x00000001) /* */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_KEY] Bits */\r
-#define FPB_FP_CTRL_KEY_OFS ( 1) /* KEY Offset */\r
-#define FPB_FP_CTRL_KEY (0x00000002) /* */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE1] Bits */\r
-#define FPB_FP_CTRL_NUM_CODE1_OFS ( 4) /* NUM_CODE1 Offset */\r
-#define FPB_FP_CTRL_NUM_CODE1_M (0x000000f0) /* */\r
-#define FPB_FP_CTRL_NUM_CODE10 (0x00000010) /* */\r
-#define FPB_FP_CTRL_NUM_CODE11 (0x00000020) /* */\r
-#define FPB_FP_CTRL_NUM_CODE12 (0x00000040) /* */\r
-#define FPB_FP_CTRL_NUM_CODE13 (0x00000080) /* */\r
-#define FPB_FP_CTRL_NUM_CODE1_0 (0x00000000) /* no code slots */\r
-#define FPB_FP_CTRL_NUM_CODE1_2 (0x00000020) /* two code slots */\r
-#define FPB_FP_CTRL_NUM_CODE1_6 (0x00000060) /* six code slots */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_LIT] Bits */\r
-#define FPB_FP_CTRL_NUM_LIT_OFS ( 8) /* NUM_LIT Offset */\r
-#define FPB_FP_CTRL_NUM_LIT_M (0x00000f00) /* */\r
-#define FPB_FP_CTRL_NUM_LIT0 (0x00000100) /* */\r
-#define FPB_FP_CTRL_NUM_LIT1 (0x00000200) /* */\r
-#define FPB_FP_CTRL_NUM_LIT2 (0x00000400) /* */\r
-#define FPB_FP_CTRL_NUM_LIT3 (0x00000800) /* */\r
-#define FPB_FP_CTRL_NUM_LIT_0 (0x00000000) /* no literal slots */\r
-#define FPB_FP_CTRL_NUM_LIT_2 (0x00000200) /* two literal slots */\r
-/* FPB_FP_CTRL[FPB_FP_CTRL_NUM_CODE2] Bits */\r
-#define FPB_FP_CTRL_NUM_CODE2_OFS (12) /* NUM_CODE2 Offset */\r
-#define FPB_FP_CTRL_NUM_CODE2_M (0x00003000) /* */\r
-/* FPB_FP_REMAP[FPB_FP_REMAP_REMAP] Bits */\r
-#define FPB_FP_REMAP_REMAP_OFS ( 5) /* REMAP Offset */\r
-#define FPB_FP_REMAP_REMAP_M (0x1fffffe0) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_ENABLE] Bits */\r
-#define FPB_FP_COMP0_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP0_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_COMP] Bits */\r
-#define FPB_FP_COMP0_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP0_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP0[FPB_FP_COMP0_REPLACE] Bits */\r
-#define FPB_FP_COMP0_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP0_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP0_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP0_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP0_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP0_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP0_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP0_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_ENABLE] Bits */\r
-#define FPB_FP_COMP1_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP1_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_COMP] Bits */\r
-#define FPB_FP_COMP1_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP1_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP1[FPB_FP_COMP1_REPLACE] Bits */\r
-#define FPB_FP_COMP1_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP1_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP1_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP1_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP1_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP1_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP1_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP1_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_ENABLE] Bits */\r
-#define FPB_FP_COMP2_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP2_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_COMP] Bits */\r
-#define FPB_FP_COMP2_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP2_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP2[FPB_FP_COMP2_REPLACE] Bits */\r
-#define FPB_FP_COMP2_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP2_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP2_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP2_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP2_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP2_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP2_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP2_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_ENABLE] Bits */\r
-#define FPB_FP_COMP3_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP3_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_COMP] Bits */\r
-#define FPB_FP_COMP3_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP3_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP3[FPB_FP_COMP3_REPLACE] Bits */\r
-#define FPB_FP_COMP3_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP3_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP3_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP3_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP3_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP3_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP3_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP3_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_ENABLE] Bits */\r
-#define FPB_FP_COMP4_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP4_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_COMP] Bits */\r
-#define FPB_FP_COMP4_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP4_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP4[FPB_FP_COMP4_REPLACE] Bits */\r
-#define FPB_FP_COMP4_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP4_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP4_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP4_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP4_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP4_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP4_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP4_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_ENABLE] Bits */\r
-#define FPB_FP_COMP5_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP5_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_COMP] Bits */\r
-#define FPB_FP_COMP5_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP5_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP5[FPB_FP_COMP5_REPLACE] Bits */\r
-#define FPB_FP_COMP5_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP5_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP5_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP5_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP5_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP5_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP5_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP5_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_ENABLE] Bits */\r
-#define FPB_FP_COMP6_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP6_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_COMP] Bits */\r
-#define FPB_FP_COMP6_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP6_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP6[FPB_FP_COMP6_REPLACE] Bits */\r
-#define FPB_FP_COMP6_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP6_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP6_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP6_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP6_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP6_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP6_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP6_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_ENABLE] Bits */\r
-#define FPB_FP_COMP7_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define FPB_FP_COMP7_ENABLE (0x00000001) /* */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_COMP] Bits */\r
-#define FPB_FP_COMP7_COMP_OFS ( 2) /* COMP Offset */\r
-#define FPB_FP_COMP7_COMP_M (0x1ffffffc) /* */\r
-/* FPB_FP_COMP7[FPB_FP_COMP7_REPLACE] Bits */\r
-#define FPB_FP_COMP7_REPLACE_OFS (30) /* REPLACE Offset */\r
-#define FPB_FP_COMP7_REPLACE_M (0xc0000000) /* */\r
-#define FPB_FP_COMP7_REPLACE0 (0x40000000) /* */\r
-#define FPB_FP_COMP7_REPLACE1 (0x80000000) /* */\r
-#define FPB_FP_COMP7_REPLACE_0 (0x00000000) /* remap to remap address. See FP_REMAP */\r
-#define FPB_FP_COMP7_REPLACE_1 (0x40000000) /* set BKPT on lower halfword, upper is unaffected */\r
-#define FPB_FP_COMP7_REPLACE_2 (0x80000000) /* set BKPT on upper halfword, lower is unaffected */\r
-#define FPB_FP_COMP7_REPLACE_3 (0xc0000000) /* set BKPT on both lower and upper halfwords. */\r
-\r
-\r
-//*****************************************************************************\r
-// FPU Bits\r
-//*****************************************************************************\r
-/* FPU_FPCCR[FPU_FPCCR_ASPEN] Bits */\r
-#define FPU_FPCCR_ASPEN_OFS (31) /* ASPEN Offset */\r
-#define FPU_FPCCR_ASPEN (0x80000000) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_LSPEN] Bits */\r
-#define FPU_FPCCR_LSPEN_OFS (30) /* LSPEN Offset */\r
-#define FPU_FPCCR_LSPEN (0x40000000) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_MONRDY] Bits */\r
-#define FPU_FPCCR_MONRDY_OFS ( 8) /* MONRDY Offset */\r
-#define FPU_FPCCR_MONRDY (0x00000100) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_BFRDY] Bits */\r
-#define FPU_FPCCR_BFRDY_OFS ( 6) /* BFRDY Offset */\r
-#define FPU_FPCCR_BFRDY (0x00000040) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_MMRDY] Bits */\r
-#define FPU_FPCCR_MMRDY_OFS ( 5) /* MMRDY Offset */\r
-#define FPU_FPCCR_MMRDY (0x00000020) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_HFRDY] Bits */\r
-#define FPU_FPCCR_HFRDY_OFS ( 4) /* HFRDY Offset */\r
-#define FPU_FPCCR_HFRDY (0x00000010) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_THREAD] Bits */\r
-#define FPU_FPCCR_THREAD_OFS ( 3) /* THREAD Offset */\r
-#define FPU_FPCCR_THREAD (0x00000008) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_USER] Bits */\r
-#define FPU_FPCCR_USER_OFS ( 1) /* USER Offset */\r
-#define FPU_FPCCR_USER (0x00000002) /* */\r
-/* FPU_FPCCR[FPU_FPCCR_LSPACT] Bits */\r
-#define FPU_FPCCR_LSPACT_OFS ( 0) /* LSPACT Offset */\r
-#define FPU_FPCCR_LSPACT (0x00000001) /* */\r
-/* FPU_FPCAR[FPU_FPCAR_ADDRESS] Bits */\r
-#define FPU_FPCAR_ADDRESS_OFS ( 2) /* ADDRESS Offset */\r
-#define FPU_FPCAR_ADDRESS_M (0x7ffffffc) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_AHP] Bits */\r
-#define FPU_FPDSCR_AHP_OFS (26) /* AHP Offset */\r
-#define FPU_FPDSCR_AHP (0x04000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_DN] Bits */\r
-#define FPU_FPDSCR_DN_OFS (25) /* DN Offset */\r
-#define FPU_FPDSCR_DN (0x02000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_FZ] Bits */\r
-#define FPU_FPDSCR_FZ_OFS (24) /* FZ Offset */\r
-#define FPU_FPDSCR_FZ (0x01000000) /* */\r
-/* FPU_FPDSCR[FPU_FPDSCR_RMODE] Bits */\r
-#define FPU_FPDSCR_RMODE_OFS (22) /* RMODE Offset */\r
-#define FPU_FPDSCR_RMODE_M (0x00c00000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_FP_ROUNDING_MODES] Bits */\r
-#define FPU_MVFR0_FP_ROUNDING_MODES_OFS (28) /* FP_ROUNDING_MODES Offset */\r
-#define FPU_MVFR0_FP_ROUNDING_MODES_M (0xf0000000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SHORT_VECTORS] Bits */\r
-#define FPU_MVFR0_SHORT_VECTORS_OFS (24) /* SHORT_VECTORS Offset */\r
-#define FPU_MVFR0_SHORT_VECTORS_M (0x0f000000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SQUARE_ROOT] Bits */\r
-#define FPU_MVFR0_SQUARE_ROOT_OFS (20) /* SQUARE_ROOT Offset */\r
-#define FPU_MVFR0_SQUARE_ROOT_M (0x00f00000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_DIVIDE] Bits */\r
-#define FPU_MVFR0_DIVIDE_OFS (16) /* DIVIDE Offset */\r
-#define FPU_MVFR0_DIVIDE_M (0x000f0000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_FP_ECEPTION_TRAPPING] Bits */\r
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_OFS (12) /* FP_EXCEPTION_TRAPPING Offset */\r
-#define FPU_MVFR0_FP_ECEPTION_TRAPPING_M (0x0000f000) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_DOUBLE_PRECISION] Bits */\r
-#define FPU_MVFR0_DOUBLE_PRECISION_OFS ( 8) /* DOUBLE_PRECISION Offset */\r
-#define FPU_MVFR0_DOUBLE_PRECISION_M (0x00000f00) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_SINGLE_PRECISION] Bits */\r
-#define FPU_MVFR0_SINGLE_PRECISION_OFS ( 4) /* SINGLE_PRECISION Offset */\r
-#define FPU_MVFR0_SINGLE_PRECISION_M (0x000000f0) /* */\r
-/* FPU_MVFR0[FPU_MVFR0_A_SIMD_REGISTERS] Bits */\r
-#define FPU_MVFR0_A_SIMD_REGISTERS_OFS ( 0) /* A_SIMD_REGISTERS Offset */\r
-#define FPU_MVFR0_A_SIMD_REGISTERS_M (0x0000000f) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FP_FUSED_MAC] Bits */\r
-#define FPU_MVFR1_FP_FUSED_MAC_OFS (28) /* FP_FUSED_MAC Offset */\r
-#define FPU_MVFR1_FP_FUSED_MAC_M (0xf0000000) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FP_HPFP] Bits */\r
-#define FPU_MVFR1_FP_HPFP_OFS (24) /* FP_HPFP Offset */\r
-#define FPU_MVFR1_FP_HPFP_M (0x0f000000) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_D_NAN_MODE] Bits */\r
-#define FPU_MVFR1_D_NAN_MODE_OFS ( 4) /* D_NAN_MODE Offset */\r
-#define FPU_MVFR1_D_NAN_MODE_M (0x000000f0) /* */\r
-/* FPU_MVFR1[FPU_MVFR1_FTZ_MODE] Bits */\r
-#define FPU_MVFR1_FTZ_MODE_OFS ( 0) /* FTZ_MODE Offset */\r
-#define FPU_MVFR1_FTZ_MODE_M (0x0000000f) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// ITM Bits\r
-//*****************************************************************************\r
-/* ITM_TPR[ITM_TPR_PRIVMASK] Bits */\r
-#define ITM_TPR_PRIVMASK_OFS ( 0) /* PRIVMASK Offset */\r
-#define ITM_TPR_PRIVMASK_M (0x0000000f) /* */\r
-/* ITM_TCR[ITM_TCR_ITMENA] Bits */\r
-#define ITM_TCR_ITMENA_OFS ( 0) /* ITMENA Offset */\r
-#define ITM_TCR_ITMENA (0x00000001) /* */\r
-/* ITM_TCR[ITM_TCR_TSENA] Bits */\r
-#define ITM_TCR_TSENA_OFS ( 1) /* TSENA Offset */\r
-#define ITM_TCR_TSENA (0x00000002) /* */\r
-/* ITM_TCR[ITM_TCR_SYNCENA] Bits */\r
-#define ITM_TCR_SYNCENA_OFS ( 2) /* SYNCENA Offset */\r
-#define ITM_TCR_SYNCENA (0x00000004) /* */\r
-/* ITM_TCR[ITM_TCR_DWTENA] Bits */\r
-#define ITM_TCR_DWTENA_OFS ( 3) /* DWTENA Offset */\r
-#define ITM_TCR_DWTENA (0x00000008) /* */\r
-/* ITM_TCR[ITM_TCR_SWOENA] Bits */\r
-#define ITM_TCR_SWOENA_OFS ( 4) /* SWOENA Offset */\r
-#define ITM_TCR_SWOENA (0x00000010) /* */\r
-/* ITM_TCR[ITM_TCR_TSPRESCALE] Bits */\r
-#define ITM_TCR_TSPRESCALE_OFS ( 8) /* TSPRESCALE Offset */\r
-#define ITM_TCR_TSPRESCALE_M (0x00000300) /* */\r
-#define ITM_TCR_TSPRESCALE0 (0x00000100) /* */\r
-#define ITM_TCR_TSPRESCALE1 (0x00000200) /* */\r
-#define ITM_TCR_TSPRESCALE_0 (0x00000000) /* no prescaling */\r
-#define ITM_TCR_TSPRESCALE_1 (0x00000100) /* divide by 4 */\r
-#define ITM_TCR_TSPRESCALE_2 (0x00000200) /* divide by 16 */\r
-#define ITM_TCR_TSPRESCALE_3 (0x00000300) /* divide by 64 */\r
-/* ITM_TCR[ITM_TCR_ATBID] Bits */\r
-#define ITM_TCR_ATBID_OFS (16) /* ATBID Offset */\r
-#define ITM_TCR_ATBID_M (0x007f0000) /* */\r
-/* ITM_TCR[ITM_TCR_BUSY] Bits */\r
-#define ITM_TCR_BUSY_OFS (23) /* BUSY Offset */\r
-#define ITM_TCR_BUSY (0x00800000) /* */\r
-/* ITM_IWR[ITM_IWR_ATVALIDM] Bits */\r
-#define ITM_IWR_ATVALIDM_OFS ( 0) /* ATVALIDM Offset */\r
-#define ITM_IWR_ATVALIDM (0x00000001) /* */\r
-/* ITM_IMCR[ITM_IMCR_INTEGRATION] Bits */\r
-#define ITM_IMCR_INTEGRATION_OFS ( 0) /* INTEGRATION Offset */\r
-#define ITM_IMCR_INTEGRATION (0x00000001) /* */\r
-/* ITM_LSR[ITM_LSR_PRESENT] Bits */\r
-#define ITM_LSR_PRESENT_OFS ( 0) /* PRESENT Offset */\r
-#define ITM_LSR_PRESENT (0x00000001) /* */\r
-/* ITM_LSR[ITM_LSR_ACCESS] Bits */\r
-#define ITM_LSR_ACCESS_OFS ( 1) /* ACCESS Offset */\r
-#define ITM_LSR_ACCESS (0x00000002) /* */\r
-/* ITM_LSR[ITM_LSR_BYTEACC] Bits */\r
-#define ITM_LSR_BYTEACC_OFS ( 2) /* BYTEACC Offset */\r
-#define ITM_LSR_BYTEACC (0x00000004) /* */\r
-\r
-\r
-//*****************************************************************************\r
-// MPU Bits\r
-//*****************************************************************************\r
-/* MPU_TYPE[MPU_TYPE_SEPARATE] Bits */\r
-#define MPU_TYPE_SEPARATE_OFS ( 0) /* SEPARATE Offset */\r
-#define MPU_TYPE_SEPARATE (0x00000001) /* */\r
-/* MPU_TYPE[MPU_TYPE_DREGION] Bits */\r
-#define MPU_TYPE_DREGION_OFS ( 8) /* DREGION Offset */\r
-#define MPU_TYPE_DREGION_M (0x0000ff00) /* */\r
-/* MPU_TYPE[MPU_TYPE_IREGION] Bits */\r
-#define MPU_TYPE_IREGION_OFS (16) /* IREGION Offset */\r
-#define MPU_TYPE_IREGION_M (0x00ff0000) /* */\r
-/* MPU_CTRL[MPU_CTRL_ENABLE] Bits */\r
-#define MPU_CTRL_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define MPU_CTRL_ENABLE (0x00000001) /* */\r
-/* MPU_CTRL[MPU_CTRL_HFNMIENA] Bits */\r
-#define MPU_CTRL_HFNMIENA_OFS ( 1) /* HFNMIENA Offset */\r
-#define MPU_CTRL_HFNMIENA (0x00000002) /* */\r
-/* MPU_CTRL[MPU_CTRL_PRIVDEFENA] Bits */\r
-#define MPU_CTRL_PRIVDEFENA_OFS ( 2) /* PRIVDEFENA Offset */\r
-#define MPU_CTRL_PRIVDEFENA (0x00000004) /* */\r
-/* MPU_RNR[MPU_RNR_REGION] Bits */\r
-#define MPU_RNR_REGION_OFS ( 0) /* REGION Offset */\r
-#define MPU_RNR_REGION_M (0x000000ff) /* */\r
-/* MPU_RBAR[MPU_RBAR_REGION] Bits */\r
-#define MPU_RBAR_REGION_OFS ( 0) /* REGION Offset */\r
-#define MPU_RBAR_REGION_M (0x0000000f) /* */\r
-/* MPU_RBAR[MPU_RBAR_VALID] Bits */\r
-#define MPU_RBAR_VALID_OFS ( 4) /* VALID Offset */\r
-#define MPU_RBAR_VALID (0x00000010) /* */\r
-/* MPU_RBAR[MPU_RBAR_ADDR] Bits */\r
-#define MPU_RBAR_ADDR_OFS ( 5) /* ADDR Offset */\r
-#define MPU_RBAR_ADDR_M (0xffffffe0) /* */\r
-/* MPU_RASR[MPU_RASR_ENABLE] Bits */\r
-#define MPU_RASR_ENABLE_OFS ( 0) /* ENABLE Offset */\r
-#define MPU_RASR_ENABLE (0x00000001) /* */\r
-/* MPU_RASR[MPU_RASR_SIZE] Bits */\r
-#define MPU_RASR_SIZE_OFS ( 1) /* SIZE Offset */\r
-#define MPU_RASR_SIZE_M (0x0000003e) /* */\r
-#define MPU_RASR_SIZE0 (0x00000002) /* */\r
-#define MPU_RASR_SIZE1 (0x00000004) /* */\r
-#define MPU_RASR_SIZE2 (0x00000008) /* */\r
-#define MPU_RASR_SIZE3 (0x00000010) /* */\r
-#define MPU_RASR_SIZE4 (0x00000020) /* */\r
-#define MPU_RASR_SIZE_0 (0x00000000) /* 4KB */\r
-#define MPU_RASR_SIZE_1 (0x00000002) /* 256MB */\r
-#define MPU_RASR_SIZE_4 (0x00000008) /* 32B */\r
-#define MPU_RASR_SIZE_5 (0x0000000a) /* 64B */\r
-#define MPU_RASR_SIZE_6 (0x0000000c) /* 128B */\r
-#define MPU_RASR_SIZE_7 (0x0000000e) /* 256B */\r
-#define MPU_RASR_SIZE_8 (0x00000010) /* 512B */\r
-#define MPU_RASR_SIZE_9 (0x00000012) /* 1KB */\r
-#define MPU_RASR_SIZE_10 (0x00000014) /* 2KB */\r
-#define MPU_RASR_SIZE_12 (0x00000018) /* 8KB */\r
-#define MPU_RASR_SIZE_13 (0x0000001a) /* 16KB */\r
-#define MPU_RASR_SIZE_14 (0x0000001c) /* 32KB */\r
-#define MPU_RASR_SIZE_15 (0x0000001e) /* 64KB */\r
-#define MPU_RASR_SIZE_16 (0x00000020) /* 128KB */\r
-#define MPU_RASR_SIZE_17 (0x00000022) /* 256KB */\r
-#define MPU_RASR_SIZE_18 (0x00000024) /* 512KB */\r
-#define MPU_RASR_SIZE_19 (0x00000026) /* 1MB */\r
-#define MPU_RASR_SIZE_20 (0x00000028) /* 2MB */\r
-#define MPU_RASR_SIZE_21 (0x0000002a) /* 4MB */\r
-#define MPU_RASR_SIZE_22 (0x0000002c) /* 8MB */\r
-#define MPU_RASR_SIZE_23 (0x0000002e) /* 16MB */\r
-#define MPU_RASR_SIZE_24 (0x00000030) /* 32MB */\r
-#define MPU_RASR_SIZE_25 (0x00000032) /* 64MB */\r
-#define MPU_RASR_SIZE_26 (0x00000034) /* 128MB */\r
-#define MPU_RASR_SIZE_28 (0x00000038) /* 512MB */\r
-#define MPU_RASR_SIZE_29 (0x0000003a) /* 1GB */\r
-#define MPU_RASR_SIZE_30 (0x0000003c) /* 2GB */\r
-#define MPU_RASR_SIZE_31 (0x0000003e) /* 4GB */\r
-/* MPU_RASR[MPU_RASR_SRD] Bits */\r
-#define MPU_RASR_SRD_OFS ( 8) /* SRD Offset */\r
-#define MPU_RASR_SRD_M (0x0000ff00) /* */\r
-/* MPU_RASR[MPU_RASR_B] Bits */\r
-#define MPU_RASR_B_OFS (16) /* B Offset */\r
-#define MPU_RASR_B (0x00010000) /* */\r
-/* MPU_RASR[MPU_RASR_C] Bits */\r
-#define MPU_RASR_C_OFS (17) /* C Offset */\r
-#define MPU_RASR_C (0x00020000) /* */\r
-/* MPU_RASR[MPU_RASR_S] Bits */\r
-#define MPU_RASR_S_OFS (18) /* S Offset */\r
-#define MPU_RASR_S (0x00040000) /* */\r
-/* MPU_RASR[MPU_RASR_TEX] Bits */\r
-#define MPU_RASR_TEX_OFS (19) /* TEX Offset */\r
-#define MPU_RASR_TEX_M (0x00380000) /* */\r
-/* MPU_RASR[MPU_RASR_AP] Bits */\r
-#define MPU_RASR_AP_OFS (24) /* AP Offset */\r
-#define MPU_RASR_AP_M (0x07000000) /* */\r
-#define MPU_RASR_AP0 (0x01000000) /* */\r
-#define MPU_RASR_AP1 (0x02000000) /* */\r
-#define MPU_RASR_AP2 (0x04000000) /* */\r
-#define MPU_RASR_AP_0 (0x00000000) /* Priviliged permissions: No access. User permissions: No access. */\r
-#define MPU_RASR_AP_1 (0x01000000) /* Priviliged permissions: Read-write. User permissions: No access. */\r
-#define MPU_RASR_AP_2 (0x02000000) /* Priviliged permissions: Read-write. User permissions: Read-only. */\r
-#define MPU_RASR_AP_3 (0x03000000) /* Priviliged permissions: Read-write. User permissions: Read-write. */\r
-#define MPU_RASR_AP_5 (0x05000000) /* Priviliged permissions: Read-only. User permissions: No access. */\r
-#define MPU_RASR_AP_6 (0x06000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */\r
-#define MPU_RASR_AP_7 (0x07000000) /* Priviliged permissions: Read-only. User permissions: Read-only. */\r
-/* MPU_RASR[MPU_RASR_XN] Bits */\r
-#define MPU_RASR_XN_OFS (28) /* XN Offset */\r
-#define MPU_RASR_XN (0x10000000) /* */\r
+#define UDMA_CHCTL_DSTINC_M ((uint32_t)0xC0000000) /* Destination Address Increment */\r
+#define UDMA_CHCTL_DSTINC_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_DSTINC_16 ((uint32_t)0x40000000) /* Half-word */\r
+#define UDMA_CHCTL_DSTINC_32 ((uint32_t)0x80000000) /* Word */\r
+#define UDMA_CHCTL_DSTINC_NONE ((uint32_t)0xC0000000) /* No increment */\r
+#define UDMA_CHCTL_DSTSIZE_M ((uint32_t)0x30000000) /* Destination Data Size */\r
+#define UDMA_CHCTL_DSTSIZE_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_DSTSIZE_16 ((uint32_t)0x10000000) /* Half-word */\r
+#define UDMA_CHCTL_DSTSIZE_32 ((uint32_t)0x20000000) /* Word */\r
+#define UDMA_CHCTL_SRCINC_M ((uint32_t)0x0C000000) /* Source Address Increment */\r
+#define UDMA_CHCTL_SRCINC_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_SRCINC_16 ((uint32_t)0x04000000) /* Half-word */\r
+#define UDMA_CHCTL_SRCINC_32 ((uint32_t)0x08000000) /* Word */\r
+#define UDMA_CHCTL_SRCINC_NONE ((uint32_t)0x0C000000) /* No increment */\r
+#define UDMA_CHCTL_SRCSIZE_M ((uint32_t)0x03000000) /* Source Data Size */\r
+#define UDMA_CHCTL_SRCSIZE_8 ((uint32_t)0x00000000) /* Byte */\r
+#define UDMA_CHCTL_SRCSIZE_16 ((uint32_t)0x01000000) /* Half-word */\r
+#define UDMA_CHCTL_SRCSIZE_32 ((uint32_t)0x02000000) /* Word */\r
+#define UDMA_CHCTL_ARBSIZE_M ((uint32_t)0x0003C000) /* Arbitration Size */\r
+#define UDMA_CHCTL_ARBSIZE_1 ((uint32_t)0x00000000) /* 1 Transfer */\r
+#define UDMA_CHCTL_ARBSIZE_2 ((uint32_t)0x00004000) /* 2 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_4 ((uint32_t)0x00008000) /* 4 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_8 ((uint32_t)0x0000C000) /* 8 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_16 ((uint32_t)0x00010000) /* 16 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_32 ((uint32_t)0x00014000) /* 32 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_64 ((uint32_t)0x00018000) /* 64 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_128 ((uint32_t)0x0001C000) /* 128 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_256 ((uint32_t)0x00020000) /* 256 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_512 ((uint32_t)0x00024000) /* 512 Transfers */\r
+#define UDMA_CHCTL_ARBSIZE_1024 ((uint32_t)0x00028000) /* 1024 Transfers */\r
+#define UDMA_CHCTL_XFERSIZE_M ((uint32_t)0x00003FF0) /* Transfer Size (minus 1) */\r
+#define UDMA_CHCTL_NXTUSEBURST ((uint32_t)0x00000008) /* Next Useburst */\r
+#define UDMA_CHCTL_XFERMODE_M ((uint32_t)0x00000007) /* uDMA Transfer Mode */\r
+#define UDMA_CHCTL_XFERMODE_STOP ((uint32_t)0x00000000) /* Stop */\r
+#define UDMA_CHCTL_XFERMODE_BASIC ((uint32_t)0x00000001) /* Basic */\r
+#define UDMA_CHCTL_XFERMODE_AUTO ((uint32_t)0x00000002) /* Auto-Request */\r
+#define UDMA_CHCTL_XFERMODE_PINGPONG ((uint32_t)0x00000003) /* Ping-Pong */\r
+#define UDMA_CHCTL_XFERMODE_MEM_SG ((uint32_t)0x00000004) /* Memory Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_MEM_SGA ((uint32_t)0x00000005) /* Alternate Memory Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_PER_SG ((uint32_t)0x00000006) /* Peripheral Scatter-Gather */\r
+#define UDMA_CHCTL_XFERMODE_PER_SGA ((uint32_t)0x00000007) /* Alternate Peripheral Scatter-Gather */\r
+\r
+#define UDMA_CHCTL_XFERSIZE_S ( 4)\r
+\r
+\r
+/******************************************************************************\r
+* DWT Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_A Bits\r
+******************************************************************************/\r
+/* EUSCI_A_CTLW0[SWRST] Bits */\r
+#define EUSCI_A_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */\r
+#define EUSCI_A_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */\r
+/* EUSCI_A_CTLW0[TXBRK] Bits */\r
+#define EUSCI_A_CTLW0_TXBRK_OFS ( 1) /**< UCTXBRK Bit Offset */\r
+#define EUSCI_A_CTLW0_TXBRK ((uint16_t)0x0002) /**< Transmit break */\r
+/* EUSCI_A_CTLW0[TXADDR] Bits */\r
+#define EUSCI_A_CTLW0_TXADDR_OFS ( 2) /**< UCTXADDR Bit Offset */\r
+#define EUSCI_A_CTLW0_TXADDR ((uint16_t)0x0004) /**< Transmit address */\r
+/* EUSCI_A_CTLW0[DORM] Bits */\r
+#define EUSCI_A_CTLW0_DORM_OFS ( 3) /**< UCDORM Bit Offset */\r
+#define EUSCI_A_CTLW0_DORM ((uint16_t)0x0008) /**< Dormant */\r
+/* EUSCI_A_CTLW0[BRKIE] Bits */\r
+#define EUSCI_A_CTLW0_BRKIE_OFS ( 4) /**< UCBRKIE Bit Offset */\r
+#define EUSCI_A_CTLW0_BRKIE ((uint16_t)0x0010) /**< Receive break character interrupt enable */\r
+/* EUSCI_A_CTLW0[RXEIE] Bits */\r
+#define EUSCI_A_CTLW0_RXEIE_OFS ( 5) /**< UCRXEIE Bit Offset */\r
+#define EUSCI_A_CTLW0_RXEIE ((uint16_t)0x0020) /**< Receive erroneous-character interrupt enable */\r
+/* EUSCI_A_CTLW0[SSEL] Bits */\r
+#define EUSCI_A_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */\r
+#define EUSCI_A_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */\r
+#define EUSCI_A_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */\r
+#define EUSCI_A_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */\r
+#define EUSCI_A_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLK */\r
+#define EUSCI_A_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_A_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_A_CTLW0_SSEL__UCLK ((uint16_t)0x0000) /**< UCLK */\r
+#define EUSCI_A_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_A_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */\r
+/* EUSCI_A_CTLW0[SYNC] Bits */\r
+#define EUSCI_A_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */\r
+#define EUSCI_A_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */\r
+/* EUSCI_A_CTLW0[MODE] Bits */\r
+#define EUSCI_A_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */\r
+#define EUSCI_A_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */\r
+#define EUSCI_A_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */\r
+#define EUSCI_A_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */\r
+#define EUSCI_A_CTLW0_MODE_0 ((uint16_t)0x0000) /**< UART mode */\r
+#define EUSCI_A_CTLW0_MODE_1 ((uint16_t)0x0200) /**< Idle-line multiprocessor mode */\r
+#define EUSCI_A_CTLW0_MODE_2 ((uint16_t)0x0400) /**< Address-bit multiprocessor mode */\r
+#define EUSCI_A_CTLW0_MODE_3 ((uint16_t)0x0600) /**< UART mode with automatic baud-rate detection */\r
+/* EUSCI_A_CTLW0[SPB] Bits */\r
+#define EUSCI_A_CTLW0_SPB_OFS (11) /**< UCSPB Bit Offset */\r
+#define EUSCI_A_CTLW0_SPB ((uint16_t)0x0800) /**< Stop bit select */\r
+/* EUSCI_A_CTLW0[SEVENBIT] Bits */\r
+#define EUSCI_A_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */\r
+#define EUSCI_A_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */\r
+/* EUSCI_A_CTLW0[MSB] Bits */\r
+#define EUSCI_A_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */\r
+#define EUSCI_A_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */\r
+/* EUSCI_A_CTLW0[PAR] Bits */\r
+#define EUSCI_A_CTLW0_PAR_OFS (14) /**< UCPAR Bit Offset */\r
+#define EUSCI_A_CTLW0_PAR ((uint16_t)0x4000) /**< Parity select */\r
+/* EUSCI_A_CTLW0[PEN] Bits */\r
+#define EUSCI_A_CTLW0_PEN_OFS (15) /**< UCPEN Bit Offset */\r
+#define EUSCI_A_CTLW0_PEN ((uint16_t)0x8000) /**< Parity enable */\r
+/* EUSCI_A_CTLW0[STEM] Bits */\r
+#define EUSCI_A_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */\r
+#define EUSCI_A_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */\r
+/* EUSCI_A_CTLW0[SSEL] Bits */\r
+\r
+\r
+#define EUSCI_A_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */\r
+\r
+\r
+/* EUSCI_A_CTLW0[MODE] Bits */\r
+\r
+\r
+\r
+/* EUSCI_A_CTLW0[MST] Bits */\r
+#define EUSCI_A_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */\r
+#define EUSCI_A_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */\r
+/* EUSCI_A_CTLW0[CKPL] Bits */\r
+#define EUSCI_A_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */\r
+#define EUSCI_A_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */\r
+/* EUSCI_A_CTLW0[CKPH] Bits */\r
+#define EUSCI_A_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */\r
+#define EUSCI_A_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */\r
+/* EUSCI_A_CTLW1[GLIT] Bits */\r
+#define EUSCI_A_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */\r
+#define EUSCI_A_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */\r
+#define EUSCI_A_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */\r
+#define EUSCI_A_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */\r
+#define EUSCI_A_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< Approximately 2 ns (equivalent of 1 delay element) */\r
+#define EUSCI_A_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< Approximately 50 ns */\r
+#define EUSCI_A_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< Approximately 100 ns */\r
+#define EUSCI_A_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< Approximately 200 ns */\r
+/* EUSCI_A_MCTLW[OS16] Bits */\r
+#define EUSCI_A_MCTLW_OS16_OFS ( 0) /**< UCOS16 Bit Offset */\r
+#define EUSCI_A_MCTLW_OS16 ((uint16_t)0x0001) /**< Oversampling mode enabled */\r
+/* EUSCI_A_MCTLW[BRF] Bits */\r
+#define EUSCI_A_MCTLW_BRF_OFS ( 4) /**< UCBRF Bit Offset */\r
+#define EUSCI_A_MCTLW_BRF_MASK ((uint16_t)0x00F0) /**< UCBRF Bit Mask */\r
+/* EUSCI_A_MCTLW[BRS] Bits */\r
+#define EUSCI_A_MCTLW_BRS_OFS ( 8) /**< UCBRS Bit Offset */\r
+#define EUSCI_A_MCTLW_BRS_MASK ((uint16_t)0xFF00) /**< UCBRS Bit Mask */\r
+/* EUSCI_A_STATW[BUSY] Bits */\r
+#define EUSCI_A_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */\r
+#define EUSCI_A_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_A busy */\r
+/* EUSCI_A_STATW[ADDR_IDLE] Bits */\r
+#define EUSCI_A_STATW_ADDR_IDLE_OFS ( 1) /**< UCADDR_UCIDLE Bit Offset */\r
+#define EUSCI_A_STATW_ADDR_IDLE ((uint16_t)0x0002) /**< Address received / Idle line detected */\r
+/* EUSCI_A_STATW[RXERR] Bits */\r
+#define EUSCI_A_STATW_RXERR_OFS ( 2) /**< UCRXERR Bit Offset */\r
+#define EUSCI_A_STATW_RXERR ((uint16_t)0x0004) /**< Receive error flag */\r
+/* EUSCI_A_STATW[BRK] Bits */\r
+#define EUSCI_A_STATW_BRK_OFS ( 3) /**< UCBRK Bit Offset */\r
+#define EUSCI_A_STATW_BRK ((uint16_t)0x0008) /**< Break detect flag */\r
+/* EUSCI_A_STATW[PE] Bits */\r
+#define EUSCI_A_STATW_PE_OFS ( 4) /**< UCPE Bit Offset */\r
+#define EUSCI_A_STATW_PE ((uint16_t)0x0010)\r
+/* EUSCI_A_STATW[OE] Bits */\r
+#define EUSCI_A_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */\r
+#define EUSCI_A_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */\r
+/* EUSCI_A_STATW[FE] Bits */\r
+#define EUSCI_A_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */\r
+#define EUSCI_A_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */\r
+/* EUSCI_A_STATW[LISTEN] Bits */\r
+#define EUSCI_A_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */\r
+#define EUSCI_A_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */\r
+/* EUSCI_A_RXBUF[RXBUF] Bits */\r
+#define EUSCI_A_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */\r
+#define EUSCI_A_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */\r
+/* EUSCI_A_TXBUF[TXBUF] Bits */\r
+#define EUSCI_A_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */\r
+#define EUSCI_A_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */\r
+/* EUSCI_A_ABCTL[ABDEN] Bits */\r
+#define EUSCI_A_ABCTL_ABDEN_OFS ( 0) /**< UCABDEN Bit Offset */\r
+#define EUSCI_A_ABCTL_ABDEN ((uint16_t)0x0001) /**< Automatic baud-rate detect enable */\r
+/* EUSCI_A_ABCTL[BTOE] Bits */\r
+#define EUSCI_A_ABCTL_BTOE_OFS ( 2) /**< UCBTOE Bit Offset */\r
+#define EUSCI_A_ABCTL_BTOE ((uint16_t)0x0004) /**< Break time out error */\r
+/* EUSCI_A_ABCTL[STOE] Bits */\r
+#define EUSCI_A_ABCTL_STOE_OFS ( 3) /**< UCSTOE Bit Offset */\r
+#define EUSCI_A_ABCTL_STOE ((uint16_t)0x0008) /**< Synch field time out error */\r
+/* EUSCI_A_ABCTL[DELIM] Bits */\r
+#define EUSCI_A_ABCTL_DELIM_OFS ( 4) /**< UCDELIM Bit Offset */\r
+#define EUSCI_A_ABCTL_DELIM_MASK ((uint16_t)0x0030) /**< UCDELIM Bit Mask */\r
+#define EUSCI_A_ABCTL_DELIM0 ((uint16_t)0x0010) /**< DELIM Bit 0 */\r
+#define EUSCI_A_ABCTL_DELIM1 ((uint16_t)0x0020) /**< DELIM Bit 1 */\r
+#define EUSCI_A_ABCTL_DELIM_0 ((uint16_t)0x0000) /**< 1 bit time */\r
+#define EUSCI_A_ABCTL_DELIM_1 ((uint16_t)0x0010) /**< 2 bit times */\r
+#define EUSCI_A_ABCTL_DELIM_2 ((uint16_t)0x0020) /**< 3 bit times */\r
+#define EUSCI_A_ABCTL_DELIM_3 ((uint16_t)0x0030) /**< 4 bit times */\r
+/* EUSCI_A_IRCTL[IREN] Bits */\r
+#define EUSCI_A_IRCTL_IREN_OFS ( 0) /**< UCIREN Bit Offset */\r
+#define EUSCI_A_IRCTL_IREN ((uint16_t)0x0001) /**< IrDA encoder/decoder enable */\r
+/* EUSCI_A_IRCTL[IRTXCLK] Bits */\r
+#define EUSCI_A_IRCTL_IRTXCLK_OFS ( 1) /**< UCIRTXCLK Bit Offset */\r
+#define EUSCI_A_IRCTL_IRTXCLK ((uint16_t)0x0002) /**< IrDA transmit pulse clock select */\r
+/* EUSCI_A_IRCTL[IRTXPL] Bits */\r
+#define EUSCI_A_IRCTL_IRTXPL_OFS ( 2) /**< UCIRTXPL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRTXPL_MASK ((uint16_t)0x00FC) /**< UCIRTXPL Bit Mask */\r
+/* EUSCI_A_IRCTL[IRRXFE] Bits */\r
+#define EUSCI_A_IRCTL_IRRXFE_OFS ( 8) /**< UCIRRXFE Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXFE ((uint16_t)0x0100) /**< IrDA receive filter enabled */\r
+/* EUSCI_A_IRCTL[IRRXPL] Bits */\r
+#define EUSCI_A_IRCTL_IRRXPL_OFS ( 9) /**< UCIRRXPL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXPL ((uint16_t)0x0200) /**< IrDA receive input UCAxRXD polarity */\r
+/* EUSCI_A_IRCTL[IRRXFL] Bits */\r
+#define EUSCI_A_IRCTL_IRRXFL_OFS (10) /**< UCIRRXFL Bit Offset */\r
+#define EUSCI_A_IRCTL_IRRXFL_MASK ((uint16_t)0x3C00) /**< UCIRRXFL Bit Mask */\r
+/* EUSCI_A_IE[RXIE] Bits */\r
+#define EUSCI_A_IE_RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_A_IE_RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_A_IE[TXIE] Bits */\r
+#define EUSCI_A_IE_TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_A_IE_TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_A_IE[STTIE] Bits */\r
+#define EUSCI_A_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */\r
+#define EUSCI_A_IE_STTIE ((uint16_t)0x0004) /**< Start bit interrupt enable */\r
+/* EUSCI_A_IE[TXCPTIE] Bits */\r
+#define EUSCI_A_IE_TXCPTIE_OFS ( 3) /**< UCTXCPTIE Bit Offset */\r
+#define EUSCI_A_IE_TXCPTIE ((uint16_t)0x0008) /**< Transmit complete interrupt enable */\r
+/* EUSCI_A_UCAxIE_SPI[RXIE] Bits */\r
+#define EUSCI_A__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_A__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_A_UCAxIE_SPI[TXIE] Bits */\r
+#define EUSCI_A__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_A__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_A_IFG[RXIFG] Bits */\r
+#define EUSCI_A_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */\r
+#define EUSCI_A_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */\r
+/* EUSCI_A_IFG[TXIFG] Bits */\r
+#define EUSCI_A_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */\r
+#define EUSCI_A_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */\r
+/* EUSCI_A_IFG[STTIFG] Bits */\r
+#define EUSCI_A_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */\r
+#define EUSCI_A_IFG_STTIFG ((uint16_t)0x0004) /**< Start bit interrupt flag */\r
+/* EUSCI_A_IFG[TXCPTIFG] Bits */\r
+#define EUSCI_A_IFG_TXCPTIFG_OFS ( 3) /**< UCTXCPTIFG Bit Offset */\r
+#define EUSCI_A_IFG_TXCPTIFG ((uint16_t)0x0008) /**< Transmit ready interrupt enable */\r
+\r
+\r
+/******************************************************************************\r
+* EUSCI_B Bits\r
+******************************************************************************/\r
+/* EUSCI_B_CTLW0[SWRST] Bits */\r
+#define EUSCI_B_CTLW0_SWRST_OFS ( 0) /**< UCSWRST Bit Offset */\r
+#define EUSCI_B_CTLW0_SWRST ((uint16_t)0x0001) /**< Software reset enable */\r
+/* EUSCI_B_CTLW0[TXSTT] Bits */\r
+#define EUSCI_B_CTLW0_TXSTT_OFS ( 1) /**< UCTXSTT Bit Offset */\r
+#define EUSCI_B_CTLW0_TXSTT ((uint16_t)0x0002) /**< Transmit START condition in master mode */\r
+/* EUSCI_B_CTLW0[TXSTP] Bits */\r
+#define EUSCI_B_CTLW0_TXSTP_OFS ( 2) /**< UCTXSTP Bit Offset */\r
+#define EUSCI_B_CTLW0_TXSTP ((uint16_t)0x0004) /**< Transmit STOP condition in master mode */\r
+/* EUSCI_B_CTLW0[TXNACK] Bits */\r
+#define EUSCI_B_CTLW0_TXNACK_OFS ( 3) /**< UCTXNACK Bit Offset */\r
+#define EUSCI_B_CTLW0_TXNACK ((uint16_t)0x0008) /**< Transmit a NACK */\r
+/* EUSCI_B_CTLW0[TR] Bits */\r
+#define EUSCI_B_CTLW0_TR_OFS ( 4) /**< UCTR Bit Offset */\r
+#define EUSCI_B_CTLW0_TR ((uint16_t)0x0010) /**< Transmitter/receiver */\r
+/* EUSCI_B_CTLW0[TXACK] Bits */\r
+#define EUSCI_B_CTLW0_TXACK_OFS ( 5) /**< UCTXACK Bit Offset */\r
+#define EUSCI_B_CTLW0_TXACK ((uint16_t)0x0020) /**< Transmit ACK condition in slave mode */\r
+/* EUSCI_B_CTLW0[SSEL] Bits */\r
+#define EUSCI_B_CTLW0_SSEL_OFS ( 6) /**< UCSSEL Bit Offset */\r
+#define EUSCI_B_CTLW0_SSEL_MASK ((uint16_t)0x00C0) /**< UCSSEL Bit Mask */\r
+#define EUSCI_B_CTLW0_SSEL0 ((uint16_t)0x0040) /**< SSEL Bit 0 */\r
+#define EUSCI_B_CTLW0_SSEL1 ((uint16_t)0x0080) /**< SSEL Bit 1 */\r
+#define EUSCI_B_CTLW0_UCSSEL_0 ((uint16_t)0x0000) /**< UCLKI */\r
+#define EUSCI_B_CTLW0_UCSSEL_1 ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_B_CTLW0_UCSSEL_2 ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_B_CTLW0_SSEL__UCLKI ((uint16_t)0x0000) /**< UCLKI */\r
+#define EUSCI_B_CTLW0_SSEL__ACLK ((uint16_t)0x0040) /**< ACLK */\r
+#define EUSCI_B_CTLW0_SSEL__SMCLK ((uint16_t)0x0080) /**< SMCLK */\r
+#define EUSCI_B_CTLW0_SSEL_3 ((uint16_t)0x00C0) /**< SMCLK */\r
+/* EUSCI_B_CTLW0[SYNC] Bits */\r
+#define EUSCI_B_CTLW0_SYNC_OFS ( 8) /**< UCSYNC Bit Offset */\r
+#define EUSCI_B_CTLW0_SYNC ((uint16_t)0x0100) /**< Synchronous mode enable */\r
+/* EUSCI_B_CTLW0[MODE] Bits */\r
+#define EUSCI_B_CTLW0_MODE_OFS ( 9) /**< UCMODE Bit Offset */\r
+#define EUSCI_B_CTLW0_MODE_MASK ((uint16_t)0x0600) /**< UCMODE Bit Mask */\r
+#define EUSCI_B_CTLW0_MODE0 ((uint16_t)0x0200) /**< MODE Bit 0 */\r
+#define EUSCI_B_CTLW0_MODE1 ((uint16_t)0x0400) /**< MODE Bit 1 */\r
+#define EUSCI_B_CTLW0_MODE_0 ((uint16_t)0x0000) /**< 3-pin SPI */\r
+#define EUSCI_B_CTLW0_MODE_1 ((uint16_t)0x0200) /**< 4-pin SPI (master or slave enabled if STE = 1) */\r
+#define EUSCI_B_CTLW0_MODE_2 ((uint16_t)0x0400) /**< 4-pin SPI (master or slave enabled if STE = 0) */\r
+#define EUSCI_B_CTLW0_MODE_3 ((uint16_t)0x0600) /**< I2C mode */\r
+/* EUSCI_B_CTLW0[MST] Bits */\r
+#define EUSCI_B_CTLW0_MST_OFS (11) /**< UCMST Bit Offset */\r
+#define EUSCI_B_CTLW0_MST ((uint16_t)0x0800) /**< Master mode select */\r
+/* EUSCI_B_CTLW0[MM] Bits */\r
+#define EUSCI_B_CTLW0_MM_OFS (13) /**< UCMM Bit Offset */\r
+#define EUSCI_B_CTLW0_MM ((uint16_t)0x2000) /**< Multi-master environment select */\r
+/* EUSCI_B_CTLW0[SLA10] Bits */\r
+#define EUSCI_B_CTLW0_SLA10_OFS (14) /**< UCSLA10 Bit Offset */\r
+#define EUSCI_B_CTLW0_SLA10 ((uint16_t)0x4000) /**< Slave addressing mode select */\r
+/* EUSCI_B_CTLW0[A10] Bits */\r
+#define EUSCI_B_CTLW0_A10_OFS (15) /**< UCA10 Bit Offset */\r
+#define EUSCI_B_CTLW0_A10 ((uint16_t)0x8000) /**< Own addressing mode select */\r
+/* EUSCI_B_CTLW0[STEM] Bits */\r
+#define EUSCI_B_CTLW0_STEM_OFS ( 1) /**< UCSTEM Bit Offset */\r
+#define EUSCI_B_CTLW0_STEM ((uint16_t)0x0002) /**< STE mode select in master mode. */\r
+/* EUSCI_B_CTLW0[SSEL] Bits */\r
+\r
+\r
+#define EUSCI_B_CTLW0_SSEL_0 ((uint16_t)0x0000) /**< Reserved */\r
+\r
+\r
+\r
+/* EUSCI_B_CTLW0[MODE] Bits */\r
+\r
+\r
+\r
+\r
+/* EUSCI_B_CTLW0[SEVENBIT] Bits */\r
+#define EUSCI_B_CTLW0_SEVENBIT_OFS (12) /**< UC7BIT Bit Offset */\r
+#define EUSCI_B_CTLW0_SEVENBIT ((uint16_t)0x1000) /**< Character length */\r
+/* EUSCI_B_CTLW0[MSB] Bits */\r
+#define EUSCI_B_CTLW0_MSB_OFS (13) /**< UCMSB Bit Offset */\r
+#define EUSCI_B_CTLW0_MSB ((uint16_t)0x2000) /**< MSB first select */\r
+/* EUSCI_B_CTLW0[CKPL] Bits */\r
+#define EUSCI_B_CTLW0_CKPL_OFS (14) /**< UCCKPL Bit Offset */\r
+#define EUSCI_B_CTLW0_CKPL ((uint16_t)0x4000) /**< Clock polarity select */\r
+/* EUSCI_B_CTLW0[CKPH] Bits */\r
+#define EUSCI_B_CTLW0_CKPH_OFS (15) /**< UCCKPH Bit Offset */\r
+#define EUSCI_B_CTLW0_CKPH ((uint16_t)0x8000) /**< Clock phase select */\r
+/* EUSCI_B_CTLW1[GLIT] Bits */\r
+#define EUSCI_B_CTLW1_GLIT_OFS ( 0) /**< UCGLIT Bit Offset */\r
+#define EUSCI_B_CTLW1_GLIT_MASK ((uint16_t)0x0003) /**< UCGLIT Bit Mask */\r
+#define EUSCI_B_CTLW1_GLIT0 ((uint16_t)0x0001) /**< GLIT Bit 0 */\r
+#define EUSCI_B_CTLW1_GLIT1 ((uint16_t)0x0002) /**< GLIT Bit 1 */\r
+#define EUSCI_B_CTLW1_GLIT_0 ((uint16_t)0x0000) /**< 50 ns */\r
+#define EUSCI_B_CTLW1_GLIT_1 ((uint16_t)0x0001) /**< 25 ns */\r
+#define EUSCI_B_CTLW1_GLIT_2 ((uint16_t)0x0002) /**< 12.5 ns */\r
+#define EUSCI_B_CTLW1_GLIT_3 ((uint16_t)0x0003) /**< 6.25 ns */\r
+/* EUSCI_B_CTLW1[ASTP] Bits */\r
+#define EUSCI_B_CTLW1_ASTP_OFS ( 2) /**< UCASTP Bit Offset */\r
+#define EUSCI_B_CTLW1_ASTP_MASK ((uint16_t)0x000C) /**< UCASTP Bit Mask */\r
+#define EUSCI_B_CTLW1_ASTP0 ((uint16_t)0x0004) /**< ASTP Bit 0 */\r
+#define EUSCI_B_CTLW1_ASTP1 ((uint16_t)0x0008) /**< ASTP Bit 1 */\r
+#define EUSCI_B_CTLW1_ASTP_0 ((uint16_t)0x0000) /**< No automatic STOP generation. The STOP condition is generated after the user */\r
+ /* sets the UCTXSTP bit. The value in UCBxTBCNT is a don't care. */\r
+#define EUSCI_B_CTLW1_ASTP_1 ((uint16_t)0x0004) /**< UCBCNTIFG is set with the byte counter reaches the threshold defined in */\r
+ /* UCBxTBCNT */\r
+#define EUSCI_B_CTLW1_ASTP_2 ((uint16_t)0x0008) /**< A STOP condition is generated automatically after the byte counter value */\r
+ /* reached UCBxTBCNT. UCBCNTIFG is set with the byte counter reaching the */\r
+ /* threshold */\r
+/* EUSCI_B_CTLW1[SWACK] Bits */\r
+#define EUSCI_B_CTLW1_SWACK_OFS ( 4) /**< UCSWACK Bit Offset */\r
+#define EUSCI_B_CTLW1_SWACK ((uint16_t)0x0010) /**< SW or HW ACK control */\r
+/* EUSCI_B_CTLW1[STPNACK] Bits */\r
+#define EUSCI_B_CTLW1_STPNACK_OFS ( 5) /**< UCSTPNACK Bit Offset */\r
+#define EUSCI_B_CTLW1_STPNACK ((uint16_t)0x0020) /**< ACK all master bytes */\r
+/* EUSCI_B_CTLW1[CLTO] Bits */\r
+#define EUSCI_B_CTLW1_CLTO_OFS ( 6) /**< UCCLTO Bit Offset */\r
+#define EUSCI_B_CTLW1_CLTO_MASK ((uint16_t)0x00C0) /**< UCCLTO Bit Mask */\r
+#define EUSCI_B_CTLW1_CLTO0 ((uint16_t)0x0040) /**< CLTO Bit 0 */\r
+#define EUSCI_B_CTLW1_CLTO1 ((uint16_t)0x0080) /**< CLTO Bit 1 */\r
+#define EUSCI_B_CTLW1_CLTO_0 ((uint16_t)0x0000) /**< Disable clock low timeout counter */\r
+#define EUSCI_B_CTLW1_CLTO_1 ((uint16_t)0x0040) /**< 135 000 SYSCLK cycles (approximately 28 ms) */\r
+#define EUSCI_B_CTLW1_CLTO_2 ((uint16_t)0x0080) /**< 150 000 SYSCLK cycles (approximately 31 ms) */\r
+#define EUSCI_B_CTLW1_CLTO_3 ((uint16_t)0x00C0) /**< 165 000 SYSCLK cycles (approximately 34 ms) */\r
+/* EUSCI_B_CTLW1[ETXINT] Bits */\r
+#define EUSCI_B_CTLW1_ETXINT_OFS ( 8) /**< UCETXINT Bit Offset */\r
+#define EUSCI_B_CTLW1_ETXINT ((uint16_t)0x0100) /**< Early UCTXIFG0 */\r
+/* EUSCI_B_STATW[BBUSY] Bits */\r
+#define EUSCI_B_STATW_BBUSY_OFS ( 4) /**< UCBBUSY Bit Offset */\r
+#define EUSCI_B_STATW_BBUSY ((uint16_t)0x0010) /**< Bus busy */\r
+/* EUSCI_B_STATW[GC] Bits */\r
+#define EUSCI_B_STATW_GC_OFS ( 5) /**< UCGC Bit Offset */\r
+#define EUSCI_B_STATW_GC ((uint16_t)0x0020) /**< General call address received */\r
+/* EUSCI_B_STATW[SCLLOW] Bits */\r
+#define EUSCI_B_STATW_SCLLOW_OFS ( 6) /**< UCSCLLOW Bit Offset */\r
+#define EUSCI_B_STATW_SCLLOW ((uint16_t)0x0040) /**< SCL low */\r
+/* EUSCI_B_STATW[BCNT] Bits */\r
+#define EUSCI_B_STATW_BCNT_OFS ( 8) /**< UCBCNT Bit Offset */\r
+#define EUSCI_B_STATW_BCNT_MASK ((uint16_t)0xFF00) /**< UCBCNT Bit Mask */\r
+/* EUSCI_B_STATW[BUSY] Bits */\r
+#define EUSCI_B_STATW_BUSY_OFS ( 0) /**< UCBUSY Bit Offset */\r
+#define EUSCI_B_STATW_BUSY ((uint16_t)0x0001) /**< eUSCI_B busy */\r
+/* EUSCI_B_STATW[OE] Bits */\r
+#define EUSCI_B_STATW_OE_OFS ( 5) /**< UCOE Bit Offset */\r
+#define EUSCI_B_STATW_OE ((uint16_t)0x0020) /**< Overrun error flag */\r
+/* EUSCI_B_STATW[FE] Bits */\r
+#define EUSCI_B_STATW_FE_OFS ( 6) /**< UCFE Bit Offset */\r
+#define EUSCI_B_STATW_FE ((uint16_t)0x0040) /**< Framing error flag */\r
+/* EUSCI_B_STATW[LISTEN] Bits */\r
+#define EUSCI_B_STATW_LISTEN_OFS ( 7) /**< UCLISTEN Bit Offset */\r
+#define EUSCI_B_STATW_LISTEN ((uint16_t)0x0080) /**< Listen enable */\r
+/* EUSCI_B_TBCNT[TBCNT] Bits */\r
+#define EUSCI_B_TBCNT_TBCNT_OFS ( 0) /**< UCTBCNT Bit Offset */\r
+#define EUSCI_B_TBCNT_TBCNT_MASK ((uint16_t)0x00FF) /**< UCTBCNT Bit Mask */\r
+/* EUSCI_B_RXBUF[RXBUF] Bits */\r
+#define EUSCI_B_RXBUF_RXBUF_OFS ( 0) /**< UCRXBUF Bit Offset */\r
+#define EUSCI_B_RXBUF_RXBUF_MASK ((uint16_t)0x00FF) /**< UCRXBUF Bit Mask */\r
+/* EUSCI_B_TXBUF[TXBUF] Bits */\r
+#define EUSCI_B_TXBUF_TXBUF_OFS ( 0) /**< UCTXBUF Bit Offset */\r
+#define EUSCI_B_TXBUF_TXBUF_MASK ((uint16_t)0x00FF) /**< UCTXBUF Bit Mask */\r
+/* EUSCI_B_I2COA0[I2COA0] Bits */\r
+#define EUSCI_B_I2COA0_I2COA0_OFS ( 0) /**< I2COA0 Bit Offset */\r
+#define EUSCI_B_I2COA0_I2COA0_MASK ((uint16_t)0x03FF) /**< I2COA0 Bit Mask */\r
+/* EUSCI_B_I2COA0[OAEN] Bits */\r
+#define EUSCI_B_I2COA0_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA0_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA0[GCEN] Bits */\r
+#define EUSCI_B_I2COA0_GCEN_OFS (15) /**< UCGCEN Bit Offset */\r
+#define EUSCI_B_I2COA0_GCEN ((uint16_t)0x8000) /**< General call response enable */\r
+/* EUSCI_B_I2COA1[I2COA1] Bits */\r
+#define EUSCI_B_I2COA1_I2COA1_OFS ( 0) /**< I2COA1 Bit Offset */\r
+#define EUSCI_B_I2COA1_I2COA1_MASK ((uint16_t)0x03FF) /**< I2COA1 Bit Mask */\r
+/* EUSCI_B_I2COA1[OAEN] Bits */\r
+#define EUSCI_B_I2COA1_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA1_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA2[I2COA2] Bits */\r
+#define EUSCI_B_I2COA2_I2COA2_OFS ( 0) /**< I2COA2 Bit Offset */\r
+#define EUSCI_B_I2COA2_I2COA2_MASK ((uint16_t)0x03FF) /**< I2COA2 Bit Mask */\r
+/* EUSCI_B_I2COA2[OAEN] Bits */\r
+#define EUSCI_B_I2COA2_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA2_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_I2COA3[I2COA3] Bits */\r
+#define EUSCI_B_I2COA3_I2COA3_OFS ( 0) /**< I2COA3 Bit Offset */\r
+#define EUSCI_B_I2COA3_I2COA3_MASK ((uint16_t)0x03FF) /**< I2COA3 Bit Mask */\r
+/* EUSCI_B_I2COA3[OAEN] Bits */\r
+#define EUSCI_B_I2COA3_OAEN_OFS (10) /**< UCOAEN Bit Offset */\r
+#define EUSCI_B_I2COA3_OAEN ((uint16_t)0x0400) /**< Own Address enable register */\r
+/* EUSCI_B_ADDRX[ADDRX] Bits */\r
+#define EUSCI_B_ADDRX_ADDRX_OFS ( 0) /**< ADDRX Bit Offset */\r
+#define EUSCI_B_ADDRX_ADDRX_MASK ((uint16_t)0x03FF) /**< ADDRX Bit Mask */\r
+/* EUSCI_B_ADDMASK[ADDMASK] Bits */\r
+#define EUSCI_B_ADDMASK_ADDMASK_OFS ( 0) /**< ADDMASK Bit Offset */\r
+#define EUSCI_B_ADDMASK_ADDMASK_MASK ((uint16_t)0x03FF) /**< ADDMASK Bit Mask */\r
+/* EUSCI_B_I2CSA[I2CSA] Bits */\r
+#define EUSCI_B_I2CSA_I2CSA_OFS ( 0) /**< I2CSA Bit Offset */\r
+#define EUSCI_B_I2CSA_I2CSA_MASK ((uint16_t)0x03FF) /**< I2CSA Bit Mask */\r
+/* EUSCI_B_IE[RXIE0] Bits */\r
+#define EUSCI_B_IE_RXIE0_OFS ( 0) /**< UCRXIE0 Bit Offset */\r
+#define EUSCI_B_IE_RXIE0 ((uint16_t)0x0001) /**< Receive interrupt enable 0 */\r
+/* EUSCI_B_IE[TXIE0] Bits */\r
+#define EUSCI_B_IE_TXIE0_OFS ( 1) /**< UCTXIE0 Bit Offset */\r
+#define EUSCI_B_IE_TXIE0 ((uint16_t)0x0002) /**< Transmit interrupt enable 0 */\r
+/* EUSCI_B_IE[STTIE] Bits */\r
+#define EUSCI_B_IE_STTIE_OFS ( 2) /**< UCSTTIE Bit Offset */\r
+#define EUSCI_B_IE_STTIE ((uint16_t)0x0004) /**< START condition interrupt enable */\r
+/* EUSCI_B_IE[STPIE] Bits */\r
+#define EUSCI_B_IE_STPIE_OFS ( 3) /**< UCSTPIE Bit Offset */\r
+#define EUSCI_B_IE_STPIE ((uint16_t)0x0008) /**< STOP condition interrupt enable */\r
+/* EUSCI_B_IE[ALIE] Bits */\r
+#define EUSCI_B_IE_ALIE_OFS ( 4) /**< UCALIE Bit Offset */\r
+#define EUSCI_B_IE_ALIE ((uint16_t)0x0010) /**< Arbitration lost interrupt enable */\r
+/* EUSCI_B_IE[NACKIE] Bits */\r
+#define EUSCI_B_IE_NACKIE_OFS ( 5) /**< UCNACKIE Bit Offset */\r
+#define EUSCI_B_IE_NACKIE ((uint16_t)0x0020) /**< Not-acknowledge interrupt enable */\r
+/* EUSCI_B_IE[BCNTIE] Bits */\r
+#define EUSCI_B_IE_BCNTIE_OFS ( 6) /**< UCBCNTIE Bit Offset */\r
+#define EUSCI_B_IE_BCNTIE ((uint16_t)0x0040) /**< Byte counter interrupt enable */\r
+/* EUSCI_B_IE[CLTOIE] Bits */\r
+#define EUSCI_B_IE_CLTOIE_OFS ( 7) /**< UCCLTOIE Bit Offset */\r
+#define EUSCI_B_IE_CLTOIE ((uint16_t)0x0080) /**< Clock low timeout interrupt enable */\r
+/* EUSCI_B_IE[RXIE1] Bits */\r
+#define EUSCI_B_IE_RXIE1_OFS ( 8) /**< UCRXIE1 Bit Offset */\r
+#define EUSCI_B_IE_RXIE1 ((uint16_t)0x0100) /**< Receive interrupt enable 1 */\r
+/* EUSCI_B_IE[TXIE1] Bits */\r
+#define EUSCI_B_IE_TXIE1_OFS ( 9) /**< UCTXIE1 Bit Offset */\r
+#define EUSCI_B_IE_TXIE1 ((uint16_t)0x0200) /**< Transmit interrupt enable 1 */\r
+/* EUSCI_B_IE[RXIE2] Bits */\r
+#define EUSCI_B_IE_RXIE2_OFS (10) /**< UCRXIE2 Bit Offset */\r
+#define EUSCI_B_IE_RXIE2 ((uint16_t)0x0400) /**< Receive interrupt enable 2 */\r
+/* EUSCI_B_IE[TXIE2] Bits */\r
+#define EUSCI_B_IE_TXIE2_OFS (11) /**< UCTXIE2 Bit Offset */\r
+#define EUSCI_B_IE_TXIE2 ((uint16_t)0x0800) /**< Transmit interrupt enable 2 */\r
+/* EUSCI_B_IE[RXIE3] Bits */\r
+#define EUSCI_B_IE_RXIE3_OFS (12) /**< UCRXIE3 Bit Offset */\r
+#define EUSCI_B_IE_RXIE3 ((uint16_t)0x1000) /**< Receive interrupt enable 3 */\r
+/* EUSCI_B_IE[TXIE3] Bits */\r
+#define EUSCI_B_IE_TXIE3_OFS (13) /**< UCTXIE3 Bit Offset */\r
+#define EUSCI_B_IE_TXIE3 ((uint16_t)0x2000) /**< Transmit interrupt enable 3 */\r
+/* EUSCI_B_IE[BIT9IE] Bits */\r
+#define EUSCI_B_IE_BIT9IE_OFS (14) /**< UCBIT9IE Bit Offset */\r
+#define EUSCI_B_IE_BIT9IE ((uint16_t)0x4000) /**< Bit position 9 interrupt enable */\r
+/* EUSCI_B_UCBxIE_SPI[RXIE] Bits */\r
+#define EUSCI_B__RXIE_OFS ( 0) /**< UCRXIE Bit Offset */\r
+#define EUSCI_B__RXIE ((uint16_t)0x0001) /**< Receive interrupt enable */\r
+/* EUSCI_B_UCBxIE_SPI[TXIE] Bits */\r
+#define EUSCI_B__TXIE_OFS ( 1) /**< UCTXIE Bit Offset */\r
+#define EUSCI_B__TXIE ((uint16_t)0x0002) /**< Transmit interrupt enable */\r
+/* EUSCI_B_IFG[RXIFG0] Bits */\r
+#define EUSCI_B_IFG_RXIFG0_OFS ( 0) /**< UCRXIFG0 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG0 ((uint16_t)0x0001) /**< eUSCI_B receive interrupt flag 0 */\r
+/* EUSCI_B_IFG[TXIFG0] Bits */\r
+#define EUSCI_B_IFG_TXIFG0_OFS ( 1) /**< UCTXIFG0 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG0 ((uint16_t)0x0002) /**< eUSCI_B transmit interrupt flag 0 */\r
+/* EUSCI_B_IFG[STTIFG] Bits */\r
+#define EUSCI_B_IFG_STTIFG_OFS ( 2) /**< UCSTTIFG Bit Offset */\r
+#define EUSCI_B_IFG_STTIFG ((uint16_t)0x0004) /**< START condition interrupt flag */\r
+/* EUSCI_B_IFG[STPIFG] Bits */\r
+#define EUSCI_B_IFG_STPIFG_OFS ( 3) /**< UCSTPIFG Bit Offset */\r
+#define EUSCI_B_IFG_STPIFG ((uint16_t)0x0008) /**< STOP condition interrupt flag */\r
+/* EUSCI_B_IFG[ALIFG] Bits */\r
+#define EUSCI_B_IFG_ALIFG_OFS ( 4) /**< UCALIFG Bit Offset */\r
+#define EUSCI_B_IFG_ALIFG ((uint16_t)0x0010) /**< Arbitration lost interrupt flag */\r
+/* EUSCI_B_IFG[NACKIFG] Bits */\r
+#define EUSCI_B_IFG_NACKIFG_OFS ( 5) /**< UCNACKIFG Bit Offset */\r
+#define EUSCI_B_IFG_NACKIFG ((uint16_t)0x0020) /**< Not-acknowledge received interrupt flag */\r
+/* EUSCI_B_IFG[BCNTIFG] Bits */\r
+#define EUSCI_B_IFG_BCNTIFG_OFS ( 6) /**< UCBCNTIFG Bit Offset */\r
+#define EUSCI_B_IFG_BCNTIFG ((uint16_t)0x0040) /**< Byte counter interrupt flag */\r
+/* EUSCI_B_IFG[CLTOIFG] Bits */\r
+#define EUSCI_B_IFG_CLTOIFG_OFS ( 7) /**< UCCLTOIFG Bit Offset */\r
+#define EUSCI_B_IFG_CLTOIFG ((uint16_t)0x0080) /**< Clock low timeout interrupt flag */\r
+/* EUSCI_B_IFG[RXIFG1] Bits */\r
+#define EUSCI_B_IFG_RXIFG1_OFS ( 8) /**< UCRXIFG1 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG1 ((uint16_t)0x0100) /**< eUSCI_B receive interrupt flag 1 */\r
+/* EUSCI_B_IFG[TXIFG1] Bits */\r
+#define EUSCI_B_IFG_TXIFG1_OFS ( 9) /**< UCTXIFG1 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG1 ((uint16_t)0x0200) /**< eUSCI_B transmit interrupt flag 1 */\r
+/* EUSCI_B_IFG[RXIFG2] Bits */\r
+#define EUSCI_B_IFG_RXIFG2_OFS (10) /**< UCRXIFG2 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG2 ((uint16_t)0x0400) /**< eUSCI_B receive interrupt flag 2 */\r
+/* EUSCI_B_IFG[TXIFG2] Bits */\r
+#define EUSCI_B_IFG_TXIFG2_OFS (11) /**< UCTXIFG2 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG2 ((uint16_t)0x0800) /**< eUSCI_B transmit interrupt flag 2 */\r
+/* EUSCI_B_IFG[RXIFG3] Bits */\r
+#define EUSCI_B_IFG_RXIFG3_OFS (12) /**< UCRXIFG3 Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG3 ((uint16_t)0x1000) /**< eUSCI_B receive interrupt flag 3 */\r
+/* EUSCI_B_IFG[TXIFG3] Bits */\r
+#define EUSCI_B_IFG_TXIFG3_OFS (13) /**< UCTXIFG3 Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG3 ((uint16_t)0x2000) /**< eUSCI_B transmit interrupt flag 3 */\r
+/* EUSCI_B_IFG[BIT9IFG] Bits */\r
+#define EUSCI_B_IFG_BIT9IFG_OFS (14) /**< UCBIT9IFG Bit Offset */\r
+#define EUSCI_B_IFG_BIT9IFG ((uint16_t)0x4000) /**< Bit position 9 interrupt flag */\r
+/* EUSCI_B_IFG[RXIFG] Bits */\r
+#define EUSCI_B_IFG_RXIFG_OFS ( 0) /**< UCRXIFG Bit Offset */\r
+#define EUSCI_B_IFG_RXIFG ((uint16_t)0x0001) /**< Receive interrupt flag */\r
+/* EUSCI_B_IFG[TXIFG] Bits */\r
+#define EUSCI_B_IFG_TXIFG_OFS ( 1) /**< UCTXIFG Bit Offset */\r
+#define EUSCI_B_IFG_TXIFG ((uint16_t)0x0002) /**< Transmit interrupt flag */\r
+\r
+\r
+/******************************************************************************\r
+* FLCTL Bits\r
+******************************************************************************/\r
+/* FLCTL_POWER_STAT[PSTAT] Bits */\r
+#define FLCTL_POWER_STAT_PSTAT_OFS ( 0) /**< PSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_PSTAT_MASK ((uint32_t)0x00000007) /**< PSTAT Bit Mask */\r
+#define FLCTL_POWER_STAT_PSTAT0 ((uint32_t)0x00000001) /**< PSTAT Bit 0 */\r
+#define FLCTL_POWER_STAT_PSTAT1 ((uint32_t)0x00000002) /**< PSTAT Bit 1 */\r
+#define FLCTL_POWER_STAT_PSTAT2 ((uint32_t)0x00000004) /**< PSTAT Bit 2 */\r
+#define FLCTL_POWER_STAT_PSTAT_0 ((uint32_t)0x00000000) /**< Flash IP in power-down mode */\r
+#define FLCTL_POWER_STAT_PSTAT_1 ((uint32_t)0x00000001) /**< Flash IP Vdd domain power-up in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_2 ((uint32_t)0x00000002) /**< PSS LDO_GOOD, IREF_OK and VREF_OK check in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_3 ((uint32_t)0x00000003) /**< Flash IP SAFE_LV check in progress */\r
+#define FLCTL_POWER_STAT_PSTAT_4 ((uint32_t)0x00000004) /**< Flash IP Active */\r
+#define FLCTL_POWER_STAT_PSTAT_5 ((uint32_t)0x00000005) /**< Flash IP Active in Low-Frequency Active and Low-Frequency LPM0 modes. */\r
+#define FLCTL_POWER_STAT_PSTAT_6 ((uint32_t)0x00000006) /**< Flash IP in Standby mode */\r
+#define FLCTL_POWER_STAT_PSTAT_7 ((uint32_t)0x00000007) /**< Flash IP in Current mirror boost state */\r
+/* FLCTL_POWER_STAT[LDOSTAT] Bits */\r
+#define FLCTL_POWER_STAT_LDOSTAT_OFS ( 3) /**< LDOSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_LDOSTAT ((uint32_t)0x00000008) /**< PSS FLDO GOOD status */\r
+/* FLCTL_POWER_STAT[VREFSTAT] Bits */\r
+#define FLCTL_POWER_STAT_VREFSTAT_OFS ( 4) /**< VREFSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_VREFSTAT ((uint32_t)0x00000010) /**< PSS VREF stable status */\r
+/* FLCTL_POWER_STAT[IREFSTAT] Bits */\r
+#define FLCTL_POWER_STAT_IREFSTAT_OFS ( 5) /**< IREFSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_IREFSTAT ((uint32_t)0x00000020) /**< PSS IREF stable status */\r
+/* FLCTL_POWER_STAT[TRIMSTAT] Bits */\r
+#define FLCTL_POWER_STAT_TRIMSTAT_OFS ( 6) /**< TRIMSTAT Bit Offset */\r
+#define FLCTL_POWER_STAT_TRIMSTAT ((uint32_t)0x00000040) /**< PSS trim done status */\r
+/* FLCTL_POWER_STAT[RD_2T] Bits */\r
+#define FLCTL_POWER_STAT_RD_2T_OFS ( 7) /**< RD_2T Bit Offset */\r
+#define FLCTL_POWER_STAT_RD_2T ((uint32_t)0x00000080) /**< Indicates if Flash is being accessed in 2T mode */\r
+/* FLCTL_BANK0_RDCTL[RD_MODE] Bits */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */\r
+/* FLCTL_BANK0_RDCTL[BUFI] Bits */\r
+#define FLCTL_BANK0_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */\r
+/* FLCTL_BANK0_RDCTL[BUFD] Bits */\r
+#define FLCTL_BANK0_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */\r
+/* FLCTL_BANK0_RDCTL[WAIT] Bits */\r
+#define FLCTL_BANK0_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */\r
+#define FLCTL_BANK0_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */\r
+/* FLCTL_BANK0_RDCTL[RD_MODE_STATUS] Bits */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */\r
+#define FLCTL_BANK0_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[RD_MODE] Bits */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_OFS ( 0) /**< RD_MODE Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_MASK ((uint32_t)0x0000000F) /**< RD_MODE Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE0 ((uint32_t)0x00000001) /**< RD_MODE Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE1 ((uint32_t)0x00000002) /**< RD_MODE Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE2 ((uint32_t)0x00000004) /**< RD_MODE Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE3 ((uint32_t)0x00000008) /**< RD_MODE Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_1 ((uint32_t)0x00000001) /**< Read Margin 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_2 ((uint32_t)0x00000002) /**< Read Margin 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_3 ((uint32_t)0x00000003) /**< Program Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_4 ((uint32_t)0x00000004) /**< Erase Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_5 ((uint32_t)0x00000005) /**< Leakage Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_9 ((uint32_t)0x00000009) /**< Read Margin 0B */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_10 ((uint32_t)0x0000000A) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[BUFI] Bits */\r
+#define FLCTL_BANK1_RDCTL_BUFI_OFS ( 4) /**< BUFI Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_BUFI ((uint32_t)0x00000010) /**< Enables read buffering feature for instruction fetches to this Bank */\r
+/* FLCTL_BANK1_RDCTL[BUFD] Bits */\r
+#define FLCTL_BANK1_RDCTL_BUFD_OFS ( 5) /**< BUFD Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_BUFD ((uint32_t)0x00000020) /**< Enables read buffering feature for data reads to this Bank */\r
+/* FLCTL_BANK1_RDCTL[RD_MODE_STATUS] Bits */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_OFS (16) /**< RD_MODE_STATUS Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_MASK ((uint32_t)0x000F0000) /**< RD_MODE_STATUS Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS0 ((uint32_t)0x00010000) /**< RD_MODE_STATUS Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS1 ((uint32_t)0x00020000) /**< RD_MODE_STATUS Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS2 ((uint32_t)0x00040000) /**< RD_MODE_STATUS Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS3 ((uint32_t)0x00080000) /**< RD_MODE_STATUS Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_0 ((uint32_t)0x00000000) /**< Normal read mode */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_1 ((uint32_t)0x00010000) /**< Read Margin 0 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_2 ((uint32_t)0x00020000) /**< Read Margin 1 */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_3 ((uint32_t)0x00030000) /**< Program Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_4 ((uint32_t)0x00040000) /**< Erase Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_5 ((uint32_t)0x00050000) /**< Leakage Verify */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_9 ((uint32_t)0x00090000) /**< Read Margin 0B */\r
+#define FLCTL_BANK1_RDCTL_RD_MODE_STATUS_10 ((uint32_t)0x000A0000) /**< Read Margin 1B */\r
+/* FLCTL_BANK1_RDCTL[WAIT] Bits */\r
+#define FLCTL_BANK1_RDCTL_WAIT_OFS (12) /**< WAIT Bit Offset */\r
+#define FLCTL_BANK1_RDCTL_WAIT_MASK ((uint32_t)0x0000F000) /**< WAIT Bit Mask */\r
+#define FLCTL_BANK1_RDCTL_WAIT0 ((uint32_t)0x00001000) /**< WAIT Bit 0 */\r
+#define FLCTL_BANK1_RDCTL_WAIT1 ((uint32_t)0x00002000) /**< WAIT Bit 1 */\r
+#define FLCTL_BANK1_RDCTL_WAIT2 ((uint32_t)0x00004000) /**< WAIT Bit 2 */\r
+#define FLCTL_BANK1_RDCTL_WAIT3 ((uint32_t)0x00008000) /**< WAIT Bit 3 */\r
+#define FLCTL_BANK1_RDCTL_WAIT_0 ((uint32_t)0x00000000) /**< 0 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_1 ((uint32_t)0x00001000) /**< 1 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_2 ((uint32_t)0x00002000) /**< 2 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_3 ((uint32_t)0x00003000) /**< 3 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_4 ((uint32_t)0x00004000) /**< 4 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_5 ((uint32_t)0x00005000) /**< 5 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_6 ((uint32_t)0x00006000) /**< 6 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_7 ((uint32_t)0x00007000) /**< 7 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_8 ((uint32_t)0x00008000) /**< 8 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_9 ((uint32_t)0x00009000) /**< 9 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_10 ((uint32_t)0x0000A000) /**< 10 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_11 ((uint32_t)0x0000B000) /**< 11 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_12 ((uint32_t)0x0000C000) /**< 12 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_13 ((uint32_t)0x0000D000) /**< 13 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_14 ((uint32_t)0x0000E000) /**< 14 wait states */\r
+#define FLCTL_BANK1_RDCTL_WAIT_15 ((uint32_t)0x0000F000) /**< 15 wait states */\r
+/* FLCTL_RDBRST_CTLSTAT[START] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of burst/compare operation */\r
+/* FLCTL_RDBRST_CTLSTAT[MEM_TYPE] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_OFS ( 1) /**< MEM_TYPE Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_MASK ((uint32_t)0x00000006) /**< MEM_TYPE Bit Mask */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE0 ((uint32_t)0x00000002) /**< MEM_TYPE Bit 0 */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE1 ((uint32_t)0x00000004) /**< MEM_TYPE Bit 1 */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */\r
+#define FLCTL_RDBRST_CTLSTAT_MEM_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */\r
+/* FLCTL_RDBRST_CTLSTAT[STOP_FAIL] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL_OFS ( 3) /**< STOP_FAIL Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_STOP_FAIL ((uint32_t)0x00000008) /**< Terminate burst/compare operation */\r
+/* FLCTL_RDBRST_CTLSTAT[DATA_CMP] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP_OFS ( 4) /**< DATA_CMP Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_DATA_CMP ((uint32_t)0x00000010) /**< Data pattern used for comparison against memory read data */\r
+/* FLCTL_RDBRST_CTLSTAT[TEST_EN] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN_OFS ( 6) /**< TEST_EN Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_TEST_EN ((uint32_t)0x00000040) /**< Enable comparison against test data compare registers */\r
+/* FLCTL_RDBRST_CTLSTAT[BRST_STAT] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_OFS (16) /**< BRST_STAT Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_MASK ((uint32_t)0x00030000) /**< BRST_STAT Bit Mask */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT0 ((uint32_t)0x00010000) /**< BRST_STAT Bit 0 */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT1 ((uint32_t)0x00020000) /**< BRST_STAT Bit 1 */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_0 ((uint32_t)0x00000000) /**< Idle */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_1 ((uint32_t)0x00010000) /**< Burst/Compare START bit written, but operation pending */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_2 ((uint32_t)0x00020000) /**< Burst/Compare in progress */\r
+#define FLCTL_RDBRST_CTLSTAT_BRST_STAT_3 ((uint32_t)0x00030000) /**< Burst complete (status of completed burst remains in this state unless */\r
+ /* explicitly cleared by SW) */\r
+/* FLCTL_RDBRST_CTLSTAT[CMP_ERR] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR_OFS (18) /**< CMP_ERR Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_CMP_ERR ((uint32_t)0x00040000) /**< Burst/Compare Operation encountered atleast one data */\r
+/* FLCTL_RDBRST_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR_OFS (19) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00080000) /**< Burst/Compare Operation was terminated due to access to */\r
+/* FLCTL_RDBRST_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_RDBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 19-16 of this register */\r
+/* FLCTL_RDBRST_STARTADDR[START_ADDRESS] Bits */\r
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */\r
+#define FLCTL_RDBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< START_ADDRESS Bit Mask */\r
+/* FLCTL_RDBRST_LEN[BURST_LENGTH] Bits */\r
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_OFS ( 0) /**< BURST_LENGTH Bit Offset */\r
+#define FLCTL_RDBRST_LEN_BURST_LENGTH_MASK ((uint32_t)0x001FFFFF) /**< BURST_LENGTH Bit Mask */\r
+/* FLCTL_RDBRST_FAILADDR[FAIL_ADDRESS] Bits */\r
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_OFS ( 0) /**< FAIL_ADDRESS Bit Offset */\r
+#define FLCTL_RDBRST_FAILADDR_FAIL_ADDRESS_MASK ((uint32_t)0x001FFFFF) /**< FAIL_ADDRESS Bit Mask */\r
+/* FLCTL_RDBRST_FAILCNT[FAIL_COUNT] Bits */\r
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_OFS ( 0) /**< FAIL_COUNT Bit Offset */\r
+#define FLCTL_RDBRST_FAILCNT_FAIL_COUNT_MASK ((uint32_t)0x0001FFFF) /**< FAIL_COUNT Bit Mask */\r
+/* FLCTL_PRG_CTLSTAT[ENABLE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_ENABLE_OFS ( 0) /**< ENABLE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_ENABLE ((uint32_t)0x00000001) /**< Master control for all word program operations */\r
+/* FLCTL_PRG_CTLSTAT[MODE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Write mode */\r
+/* FLCTL_PRG_CTLSTAT[VER_PRE] Bits */\r
+#define FLCTL_PRG_CTLSTAT_VER_PRE_OFS ( 2) /**< VER_PRE Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_VER_PRE ((uint32_t)0x00000004) /**< Controls automatic pre program verify operations */\r
+/* FLCTL_PRG_CTLSTAT[VER_PST] Bits */\r
+#define FLCTL_PRG_CTLSTAT_VER_PST_OFS ( 3) /**< VER_PST Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_VER_PST ((uint32_t)0x00000008) /**< Controls automatic post program verify operations */\r
+/* FLCTL_PRG_CTLSTAT[STATUS] Bits */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */\r
+#define FLCTL_PRG_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */\r
+#define FLCTL_PRG_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Single word program operation triggered, but pending */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Single word program in progress */\r
+#define FLCTL_PRG_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Reserved (Idle) */\r
+/* FLCTL_PRG_CTLSTAT[BNK_ACT] Bits */\r
+#define FLCTL_PRG_CTLSTAT_BNK_ACT_OFS (18) /**< BNK_ACT Bit Offset */\r
+#define FLCTL_PRG_CTLSTAT_BNK_ACT ((uint32_t)0x00040000) /**< Bank active */\r
+/* FLCTL_PRGBRST_CTLSTAT[START] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_START ((uint32_t)0x00000001) /**< Trigger start of burst program operation */\r
+/* FLCTL_PRGBRST_CTLSTAT[TYPE] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_OFS ( 1) /**< TYPE Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_MASK ((uint32_t)0x00000006) /**< TYPE Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE0 ((uint32_t)0x00000002) /**< TYPE Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE1 ((uint32_t)0x00000004) /**< TYPE Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_1 ((uint32_t)0x00000002) /**< Information Memory */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_2 ((uint32_t)0x00000004) /**< Reserved */\r
+#define FLCTL_PRGBRST_CTLSTAT_TYPE_3 ((uint32_t)0x00000006) /**< Engineering Memory */\r
+/* FLCTL_PRGBRST_CTLSTAT[LEN] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_OFS ( 3) /**< LEN Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_MASK ((uint32_t)0x00000038) /**< LEN Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN0 ((uint32_t)0x00000008) /**< LEN Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN1 ((uint32_t)0x00000010) /**< LEN Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN2 ((uint32_t)0x00000020) /**< LEN Bit 2 */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_0 ((uint32_t)0x00000000) /**< No burst operation */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_1 ((uint32_t)0x00000008) /**< 1 word burst of 128 bits, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_2 ((uint32_t)0x00000010) /**< 2*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_3 ((uint32_t)0x00000018) /**< 3*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+#define FLCTL_PRGBRST_CTLSTAT_LEN_4 ((uint32_t)0x00000020) /**< 4*128 bits burst write, starting with address in the FLCTL_PRGBRST_STARTADDR */\r
+ /* Register */\r
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PRE] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE_OFS ( 6) /**< AUTO_PRE Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PRE ((uint32_t)0x00000040) /**< Auto-Verify operation before the Burst Program */\r
+/* FLCTL_PRGBRST_CTLSTAT[AUTO_PST] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST_OFS ( 7) /**< AUTO_PST Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_AUTO_PST ((uint32_t)0x00000080) /**< Auto-Verify operation after the Burst Program */\r
+/* FLCTL_PRGBRST_CTLSTAT[BURST_STATUS] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_OFS (16) /**< BURST_STATUS Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_MASK ((uint32_t)0x00070000) /**< BURST_STATUS Bit Mask */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS0 ((uint32_t)0x00010000) /**< BURST_STATUS Bit 0 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS1 ((uint32_t)0x00020000) /**< BURST_STATUS Bit 1 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS2 ((uint32_t)0x00040000) /**< BURST_STATUS Bit 2 */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_0 ((uint32_t)0x00000000) /**< Idle (Burst not active) */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_1 ((uint32_t)0x00010000) /**< Burst program started but pending */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_2 ((uint32_t)0x00020000) /**< Burst active, with 1st 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_3 ((uint32_t)0x00030000) /**< Burst active, with 2nd 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_4 ((uint32_t)0x00040000) /**< Burst active, with 3rd 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_5 ((uint32_t)0x00050000) /**< Burst active, with 4th 128 bit word being written into Flash */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_6 ((uint32_t)0x00060000) /**< Reserved (Idle) */\r
+#define FLCTL_PRGBRST_CTLSTAT_BURST_STATUS_7 ((uint32_t)0x00070000) /**< Burst Complete (status of completed burst remains in this state unless */\r
+ /* explicitly cleared by SW) */\r
+/* FLCTL_PRGBRST_CTLSTAT[PRE_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR_OFS (19) /**< PRE_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_PRE_ERR ((uint32_t)0x00080000) /**< Burst Operation encountered preprogram auto-verify errors */\r
+/* FLCTL_PRGBRST_CTLSTAT[PST_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR_OFS (20) /**< PST_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_PST_ERR ((uint32_t)0x00100000) /**< Burst Operation encountered postprogram auto-verify errors */\r
+/* FLCTL_PRGBRST_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR_OFS (21) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_ADDR_ERR ((uint32_t)0x00200000) /**< Burst Operation was terminated due to attempted program of reserved memory */\r
+/* FLCTL_PRGBRST_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT_OFS (23) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_PRGBRST_CTLSTAT_CLR_STAT ((uint32_t)0x00800000) /**< Clear status bits 21-16 of this register */\r
+/* FLCTL_PRGBRST_STARTADDR[START_ADDRESS] Bits */\r
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_OFS ( 0) /**< START_ADDRESS Bit Offset */\r
+#define FLCTL_PRGBRST_STARTADDR_START_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< START_ADDRESS Bit Mask */\r
+/* FLCTL_ERASE_CTLSTAT[START] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_START_OFS ( 0) /**< START Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_START ((uint32_t)0x00000001) /**< Start of Erase operation */\r
+/* FLCTL_ERASE_CTLSTAT[MODE] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_MODE_OFS ( 1) /**< MODE Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_MODE ((uint32_t)0x00000002) /**< Erase mode selected by application */\r
+/* FLCTL_ERASE_CTLSTAT[TYPE] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_OFS ( 2) /**< TYPE Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_MASK ((uint32_t)0x0000000C) /**< TYPE Bit Mask */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE0 ((uint32_t)0x00000004) /**< TYPE Bit 0 */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE1 ((uint32_t)0x00000008) /**< TYPE Bit 1 */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_0 ((uint32_t)0x00000000) /**< Main Memory */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_1 ((uint32_t)0x00000004) /**< Information Memory */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_2 ((uint32_t)0x00000008) /**< Reserved */\r
+#define FLCTL_ERASE_CTLSTAT_TYPE_3 ((uint32_t)0x0000000C) /**< Engineering Memory */\r
+/* FLCTL_ERASE_CTLSTAT[STATUS] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_OFS (16) /**< STATUS Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_MASK ((uint32_t)0x00030000) /**< STATUS Bit Mask */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS0 ((uint32_t)0x00010000) /**< STATUS Bit 0 */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS1 ((uint32_t)0x00020000) /**< STATUS Bit 1 */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_0 ((uint32_t)0x00000000) /**< Idle (no program operation currently active) */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_1 ((uint32_t)0x00010000) /**< Erase operation triggered to START but pending */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_2 ((uint32_t)0x00020000) /**< Erase operation in progress */\r
+#define FLCTL_ERASE_CTLSTAT_STATUS_3 ((uint32_t)0x00030000) /**< Erase operation completed (status of completed erase remains in this state */\r
+ /* unless explicitly cleared by SW) */\r
+/* FLCTL_ERASE_CTLSTAT[ADDR_ERR] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR_OFS (18) /**< ADDR_ERR Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_ADDR_ERR ((uint32_t)0x00040000) /**< Erase Operation was terminated due to attempted erase of reserved memory */\r
+ /* address */\r
+/* FLCTL_ERASE_CTLSTAT[CLR_STAT] Bits */\r
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT_OFS (19) /**< CLR_STAT Bit Offset */\r
+#define FLCTL_ERASE_CTLSTAT_CLR_STAT ((uint32_t)0x00080000) /**< Clear status bits 18-16 of this register */\r
+/* FLCTL_ERASE_SECTADDR[SECT_ADDRESS] Bits */\r
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_OFS ( 0) /**< SECT_ADDRESS Bit Offset */\r
+#define FLCTL_ERASE_SECTADDR_SECT_ADDRESS_MASK ((uint32_t)0x003FFFFF) /**< SECT_ADDRESS Bit Mask */\r
+/* FLCTL_BANK0_INFO_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */\r
+/* FLCTL_BANK0_INFO_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK0_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT2] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT3] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT4] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT5] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT6] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT7] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT8] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT9] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT10] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT11] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT12] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT13] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT14] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT15] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT16] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT17] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT18] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT19] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT20] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT21] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT22] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT23] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT24] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT25] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT26] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT27] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT28] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT29] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT30] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase */\r
+/* FLCTL_BANK0_MAIN_WEPROT[PROT31] Bits */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */\r
+#define FLCTL_BANK0_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase */\r
+/* FLCTL_BANK1_INFO_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */\r
+/* FLCTL_BANK1_INFO_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK1_INFO_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT0] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0_OFS ( 0) /**< PROT0 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT0 ((uint32_t)0x00000001) /**< Protects Sector 0 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT1] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1_OFS ( 1) /**< PROT1 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT1 ((uint32_t)0x00000002) /**< Protects Sector 1 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT2] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2_OFS ( 2) /**< PROT2 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT2 ((uint32_t)0x00000004) /**< Protects Sector 2 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT3] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3_OFS ( 3) /**< PROT3 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT3 ((uint32_t)0x00000008) /**< Protects Sector 3 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT4] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4_OFS ( 4) /**< PROT4 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT4 ((uint32_t)0x00000010) /**< Protects Sector 4 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT5] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5_OFS ( 5) /**< PROT5 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT5 ((uint32_t)0x00000020) /**< Protects Sector 5 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT6] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6_OFS ( 6) /**< PROT6 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT6 ((uint32_t)0x00000040) /**< Protects Sector 6 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT7] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7_OFS ( 7) /**< PROT7 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT7 ((uint32_t)0x00000080) /**< Protects Sector 7 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT8] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8_OFS ( 8) /**< PROT8 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT8 ((uint32_t)0x00000100) /**< Protects Sector 8 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT9] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9_OFS ( 9) /**< PROT9 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT9 ((uint32_t)0x00000200) /**< Protects Sector 9 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT10] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10_OFS (10) /**< PROT10 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT10 ((uint32_t)0x00000400) /**< Protects Sector 10 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT11] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11_OFS (11) /**< PROT11 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT11 ((uint32_t)0x00000800) /**< Protects Sector 11 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT12] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12_OFS (12) /**< PROT12 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT12 ((uint32_t)0x00001000) /**< Protects Sector 12 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT13] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13_OFS (13) /**< PROT13 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT13 ((uint32_t)0x00002000) /**< Protects Sector 13 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT14] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14_OFS (14) /**< PROT14 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT14 ((uint32_t)0x00004000) /**< Protects Sector 14 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT15] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15_OFS (15) /**< PROT15 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT15 ((uint32_t)0x00008000) /**< Protects Sector 15 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT16] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16_OFS (16) /**< PROT16 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT16 ((uint32_t)0x00010000) /**< Protects Sector 16 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT17] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17_OFS (17) /**< PROT17 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT17 ((uint32_t)0x00020000) /**< Protects Sector 17 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT18] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18_OFS (18) /**< PROT18 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT18 ((uint32_t)0x00040000) /**< Protects Sector 18 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT19] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19_OFS (19) /**< PROT19 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT19 ((uint32_t)0x00080000) /**< Protects Sector 19 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT20] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20_OFS (20) /**< PROT20 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT20 ((uint32_t)0x00100000) /**< Protects Sector 20 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT21] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21_OFS (21) /**< PROT21 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT21 ((uint32_t)0x00200000) /**< Protects Sector 21 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT22] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22_OFS (22) /**< PROT22 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT22 ((uint32_t)0x00400000) /**< Protects Sector 22 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT23] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23_OFS (23) /**< PROT23 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT23 ((uint32_t)0x00800000) /**< Protects Sector 23 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT24] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24_OFS (24) /**< PROT24 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT24 ((uint32_t)0x01000000) /**< Protects Sector 24 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT25] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25_OFS (25) /**< PROT25 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT25 ((uint32_t)0x02000000) /**< Protects Sector 25 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT26] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26_OFS (26) /**< PROT26 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT26 ((uint32_t)0x04000000) /**< Protects Sector 26 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT27] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27_OFS (27) /**< PROT27 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT27 ((uint32_t)0x08000000) /**< Protects Sector 27 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT28] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28_OFS (28) /**< PROT28 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT28 ((uint32_t)0x10000000) /**< Protects Sector 28 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT29] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29_OFS (29) /**< PROT29 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT29 ((uint32_t)0x20000000) /**< Protects Sector 29 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT30] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30_OFS (30) /**< PROT30 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT30 ((uint32_t)0x40000000) /**< Protects Sector 30 from program or erase operations */\r
+/* FLCTL_BANK1_MAIN_WEPROT[PROT31] Bits */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31_OFS (31) /**< PROT31 Bit Offset */\r
+#define FLCTL_BANK1_MAIN_WEPROT_PROT31 ((uint32_t)0x80000000) /**< Protects Sector 31 from program or erase operations */\r
+/* FLCTL_BMRK_CTLSTAT[I_BMRK] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_I_BMRK_OFS ( 0) /**< I_BMRK Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_I_BMRK ((uint32_t)0x00000001)\r
+/* FLCTL_BMRK_CTLSTAT[D_BMRK] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_D_BMRK_OFS ( 1) /**< D_BMRK Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_D_BMRK ((uint32_t)0x00000002)\r
+/* FLCTL_BMRK_CTLSTAT[CMP_EN] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_EN_OFS ( 2) /**< CMP_EN Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_EN ((uint32_t)0x00000004)\r
+/* FLCTL_BMRK_CTLSTAT[CMP_SEL] Bits */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL_OFS ( 3) /**< CMP_SEL Bit Offset */\r
+#define FLCTL_BMRK_CTLSTAT_CMP_SEL ((uint32_t)0x00000008)\r
+/* FLCTL_IFG[RDBRST] Bits */\r
+#define FLCTL_IFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_IFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_IFG[AVPRE] Bits */\r
+#define FLCTL_IFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_IFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_IFG[AVPST] Bits */\r
+#define FLCTL_IFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_IFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_IFG[PRG] Bits */\r
+#define FLCTL_IFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_IFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_IFG[PRGB] Bits */\r
+#define FLCTL_IFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_IFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_IFG[ERASE] Bits */\r
+#define FLCTL_IFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_IFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_IFG[BMRK] Bits */\r
+#define FLCTL_IFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_IFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_IFG[PRG_ERR] Bits */\r
+#define FLCTL_IFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_IFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_IE[RDBRST] Bits */\r
+#define FLCTL_IE_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_IE_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_IE[AVPRE] Bits */\r
+#define FLCTL_IE_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_IE_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_IE[AVPST] Bits */\r
+#define FLCTL_IE_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_IE_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_IE[PRG] Bits */\r
+#define FLCTL_IE_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_IE_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_IE[PRGB] Bits */\r
+#define FLCTL_IE_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_IE_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_IE[ERASE] Bits */\r
+#define FLCTL_IE_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_IE_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_IE[BMRK] Bits */\r
+#define FLCTL_IE_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_IE_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_IE[PRG_ERR] Bits */\r
+#define FLCTL_IE_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_IE_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_CLRIFG[RDBRST] Bits */\r
+#define FLCTL_CLRIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_CLRIFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_CLRIFG[AVPRE] Bits */\r
+#define FLCTL_CLRIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_CLRIFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_CLRIFG[AVPST] Bits */\r
+#define FLCTL_CLRIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_CLRIFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_CLRIFG[PRG] Bits */\r
+#define FLCTL_CLRIFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_CLRIFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_CLRIFG[PRGB] Bits */\r
+#define FLCTL_CLRIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_CLRIFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_CLRIFG[ERASE] Bits */\r
+#define FLCTL_CLRIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_CLRIFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_CLRIFG[BMRK] Bits */\r
+#define FLCTL_CLRIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_CLRIFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_CLRIFG[PRG_ERR] Bits */\r
+#define FLCTL_CLRIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_CLRIFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_SETIFG[RDBRST] Bits */\r
+#define FLCTL_SETIFG_RDBRST_OFS ( 0) /**< RDBRST Bit Offset */\r
+#define FLCTL_SETIFG_RDBRST ((uint32_t)0x00000001)\r
+/* FLCTL_SETIFG[AVPRE] Bits */\r
+#define FLCTL_SETIFG_AVPRE_OFS ( 1) /**< AVPRE Bit Offset */\r
+#define FLCTL_SETIFG_AVPRE ((uint32_t)0x00000002)\r
+/* FLCTL_SETIFG[AVPST] Bits */\r
+#define FLCTL_SETIFG_AVPST_OFS ( 2) /**< AVPST Bit Offset */\r
+#define FLCTL_SETIFG_AVPST ((uint32_t)0x00000004)\r
+/* FLCTL_SETIFG[PRG] Bits */\r
+#define FLCTL_SETIFG_PRG_OFS ( 3) /**< PRG Bit Offset */\r
+#define FLCTL_SETIFG_PRG ((uint32_t)0x00000008)\r
+/* FLCTL_SETIFG[PRGB] Bits */\r
+#define FLCTL_SETIFG_PRGB_OFS ( 4) /**< PRGB Bit Offset */\r
+#define FLCTL_SETIFG_PRGB ((uint32_t)0x00000010)\r
+/* FLCTL_SETIFG[ERASE] Bits */\r
+#define FLCTL_SETIFG_ERASE_OFS ( 5) /**< ERASE Bit Offset */\r
+#define FLCTL_SETIFG_ERASE ((uint32_t)0x00000020)\r
+/* FLCTL_SETIFG[BMRK] Bits */\r
+#define FLCTL_SETIFG_BMRK_OFS ( 8) /**< BMRK Bit Offset */\r
+#define FLCTL_SETIFG_BMRK ((uint32_t)0x00000100)\r
+/* FLCTL_SETIFG[PRG_ERR] Bits */\r
+#define FLCTL_SETIFG_PRG_ERR_OFS ( 9) /**< PRG_ERR Bit Offset */\r
+#define FLCTL_SETIFG_PRG_ERR ((uint32_t)0x00000200)\r
+/* FLCTL_READ_TIMCTL[SETUP] Bits */\r
+#define FLCTL_READ_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_READ_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_READ_TIMCTL[IREF_BOOST1] Bits */\r
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_OFS (12) /**< IREF_BOOST1 Bit Offset */\r
+#define FLCTL_READ_TIMCTL_IREF_BOOST1_MASK ((uint32_t)0x0000F000) /**< IREF_BOOST1 Bit Mask */\r
+/* FLCTL_READ_TIMCTL[SETUP_LONG] Bits */\r
+#define FLCTL_READ_TIMCTL_SETUP_LONG_OFS (16) /**< SETUP_LONG Bit Offset */\r
+#define FLCTL_READ_TIMCTL_SETUP_LONG_MASK ((uint32_t)0x00FF0000) /**< SETUP_LONG Bit Mask */\r
+/* FLCTL_READMARGIN_TIMCTL[SETUP] Bits */\r
+#define FLCTL_READMARGIN_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_READMARGIN_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_ACTIVE_MASK ((uint32_t)0x00000F00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_PRGVER_TIMCTL[HOLD] Bits */\r
+#define FLCTL_PRGVER_TIMCTL_HOLD_OFS (12) /**< HOLD Bit Offset */\r
+#define FLCTL_PRGVER_TIMCTL_HOLD_MASK ((uint32_t)0x0000F000) /**< HOLD Bit Mask */\r
+/* FLCTL_ERSVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_ERSVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_ERSVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_LKGVER_TIMCTL[SETUP] Bits */\r
+#define FLCTL_LKGVER_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_LKGVER_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[SETUP] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_PROGRAM_TIMCTL[HOLD] Bits */\r
+#define FLCTL_PROGRAM_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */\r
+#define FLCTL_PROGRAM_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[SETUP] Bits */\r
+#define FLCTL_ERASE_TIMCTL_SETUP_OFS ( 0) /**< SETUP Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_SETUP_MASK ((uint32_t)0x000000FF) /**< SETUP Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_ERASE_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+/* FLCTL_ERASE_TIMCTL[HOLD] Bits */\r
+#define FLCTL_ERASE_TIMCTL_HOLD_OFS (28) /**< HOLD Bit Offset */\r
+#define FLCTL_ERASE_TIMCTL_HOLD_MASK ((uint32_t)0xF0000000) /**< HOLD Bit Mask */\r
+/* FLCTL_MASSERASE_TIMCTL[BOOST_ACTIVE] Bits */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_OFS ( 0) /**< BOOST_ACTIVE Bit Offset */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_ACTIVE_MASK ((uint32_t)0x000000FF) /**< BOOST_ACTIVE Bit Mask */\r
+/* FLCTL_MASSERASE_TIMCTL[BOOST_HOLD] Bits */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_OFS ( 8) /**< BOOST_HOLD Bit Offset */\r
+#define FLCTL_MASSERASE_TIMCTL_BOOST_HOLD_MASK ((uint32_t)0x0000FF00) /**< BOOST_HOLD Bit Mask */\r
+/* FLCTL_BURSTPRG_TIMCTL[ACTIVE] Bits */\r
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_OFS ( 8) /**< ACTIVE Bit Offset */\r
+#define FLCTL_BURSTPRG_TIMCTL_ACTIVE_MASK ((uint32_t)0x0FFFFF00) /**< ACTIVE Bit Mask */\r
+\r
+\r
+/******************************************************************************\r
+* FPB Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* FPU Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* ITM Bits\r
+******************************************************************************/\r
+\r
+\r
+/******************************************************************************\r
+* MPU Bits\r
+******************************************************************************/\r