The sh7757lcr has 2GByte eMMC chip. This patch supports it.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
+int board_mmc_init(bd_t *bis)
+{
+ return mmcif_mmc_init();
+}
+
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
struct spi_flash *spi;
static int get_sh_eth_mac_raw(unsigned char *buf, int size)
{
struct spi_flash *spi;
- SPI ROM 8MB
- 2D Graphic controller
- Ethernet controller
- SPI ROM 8MB
- 2D Graphic controller
- Ethernet controller
configuration for This board:
configuration for This board:
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 3
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO 1
+/* MMCIF */
+#define CONFIG_MMC 1
+#define CONFIG_GENERIC_MMC 1
+#define CONFIG_SH_MMCIF 1
+#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
+#define CONFIG_SH_MMCIF_CLK 48000000
+
/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
#define SH7757LCR_GRA_OFFSET 0x1f000000
/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
#define SH7757LCR_GRA_OFFSET 0x1f000000