- ulong uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- /* 440 GX uses base uic register */
- uic_msr = mfdcr(uicb0msr);
-
- if ( (UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr) )
- uic0_interrupt(0);
-
- if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
- uic1_interrupt(0);
-
- if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
- uic2_interrupt(0);
-
- mtdcr(uicb0sr, uic_msr);
-
- return;
-
-} /* external_interrupt CONFIG_440GX */
-
-#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
-void external_interrupt(struct pt_regs *regs)
-{
- ulong uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- /* 440 SPe uses base uic register */
- uic_msr = mfdcr(uic0msr);
-
- if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
- uic1_interrupt(0);
-
- if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
- uic2_interrupt(0);
-
- if (uic_msr & ~(UICB0_ALL))
- uic0_interrupt(0);
-
- mtdcr(uic0sr, uic_msr);
-
- return;
-
-} /* external_interrupt CONFIG_440EPX & CONFIG_440GRX */
-
-#elif defined(CONFIG_440SPE)
-void external_interrupt(struct pt_regs *regs)
-{
- ulong uic_msr;
-
- /*
- * Read masked interrupt status register to determine interrupt source
- */
- /* 440 SPe uses base uic register */
- uic_msr = mfdcr(uic0msr);
-
- if ( (UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr) )
- uic1_interrupt(0);
-
- if ( (UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr) )
- uic2_interrupt(0);
-
- if ( (UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr) )
- uic3_interrupt(0);
-
- if (uic_msr & ~(UICB0_ALL))
- uic0_interrupt(0);
-
- mtdcr(uic0sr, uic_msr);
-
- return;
-} /* external_interrupt CONFIG_440SPE */
-
-#else
-
-void external_interrupt(struct pt_regs *regs)
-{
- ulong uic_msr;
- ulong msr_shift;