This patch moves the definition for the PPC4xx NAND FLASH controller
(NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the
upcoming fix for the ECC byte ordering of the NDFC driver.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>
/*
* Overview:
* Platform independend driver for NDFC (NanD Flash Controller)
/*
* Overview:
* Platform independend driver for NDFC (NanD Flash Controller)
- * integrated into EP440 cores
+ * integrated into IBM/AMCC PPC4xx cores
- * (C) Copyright 2006-2007
+ * (C) Copyright 2006-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on original work by
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* Based on original work by
#include <common.h>
#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
#include <common.h>
#if defined(CONFIG_CMD_NAND) && !defined(CONFIG_NAND_LEGACY) && \
- (defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
- defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
- defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
- defined(CONFIG_460EX) || defined(CONFIG_460GT))
+ defined(CONFIG_NAND_NDFC)
#include <nand.h>
#include <linux/mtd/ndfc.h>
#include <nand.h>
#include <linux/mtd/ndfc.h>
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
#endif
#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
#endif
+#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
+ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
+ defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \
+ defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CONFIG_NAND_NDFC
+#endif
+
/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
#if defined(CONFIG_405EX) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */
#if defined(CONFIG_405EX) || \
defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \