i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to
access it.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <ssbabic@denx.de>
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
mmdc1->entry = value; \
} while (0)
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
- if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
+ if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */