+
+void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
+{
+ int index = tegra_pcie_port_index_of_port(port);
+
+ if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
+ tegra_pcie_port_reset(port);
+ }
+#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
+ /*
+ * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
+ * 0 share the same RESET_MOCI therefore only assert it once for both
+ * ports to avoid losing the previously brought up port again.
+ */
+ else if ((index == 1) || (index == 0)) {
+ /* only do it once per init cycle */
+ if (pci_reset_status % 2 == 0) {
+ /*
+ * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
+ * Apalis Evaluation Board
+ */
+ gpio_direction_output(PEX_PERST_N, 0);
+ gpio_direction_output(RESET_MOCI_CTRL, 0);
+
+ /*
+ * Must be asserted for 100 ms after power and clocks
+ * are stable
+ */
+ mdelay(100);
+
+ gpio_set_value(PEX_PERST_N, 1);
+ /*
+ * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
+ * Guaranteed Until 900 us After PEX_PERST# De-assertion
+ */
+ mdelay(1);
+ gpio_set_value(RESET_MOCI_CTRL, 1);
+ }
+ pci_reset_status++;
+ }
+#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
+}