Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.
Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
trans->bytesin -= bytes;
}
trans->bytesin -= bytes;
}
+static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
+{
+ if (plat->ich_version == ICHV_7) {
+ struct ich7_spi_regs *ich7_spi = sbase;
+
+ setbits_le16(&ich7_spi->spis, SPIS_LOCK);
+ } else if (plat->ich_version == ICHV_9) {
+ struct ich9_spi_regs *ich9_spi = sbase;
+
+ setbits_le16(&ich9_spi->hsfs, HSFS_FLOCKDN);
+ }
+}
+
static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
{
int lock = 0;
static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
{
int lock = 0;
+ /* Lock down SPI controller settings if required */
+ if (plat->lockdown) {
+ ich_spi_config_opcode(dev);
+ spi_lock_down(plat, priv->base);
+ }
+
priv->cur_speed = priv->max_speed;
return 0;
priv->cur_speed = priv->max_speed;
return 0;
plat->ich_version = ICHV_9;
}
plat->ich_version = ICHV_9;
}
+ plat->lockdown = fdtdec_get_bool(gd->fdt_blob, node,
+ "intel,spi-lock-down");
+
struct ich_spi_platdata {
enum ich_version ich_version; /* Controller version, 7 or 9 */
struct ich_spi_platdata {
enum ich_version ich_version; /* Controller version, 7 or 9 */
+ bool lockdown; /* lock down controller settings? */