+#ifndef __VEXPRESS_COMMON_H
+#define __VEXPRESS_COMMON_H
+
+/*
+ * Definitions copied from linux kernel:
+ * arch/arm/mach-vexpress/include/mach/motherboard.h
+ */
+#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
+/* CS register bases for the original memory map. */
+#define V2M_PA_CS0 0x40000000
+#define V2M_PA_CS1 0x44000000
+#define V2M_PA_CS2 0x48000000
+#define V2M_PA_CS3 0x4c000000
+#define V2M_PA_CS7 0x10000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 12)
+#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
+#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+
+#define V2M_BASE 0x60000000
+#define CONFIG_SYS_TEXT_BASE 0x60800000
+#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
+/* CS register bases for the extended memory map. */
+#define V2M_PA_CS0 0x08000000
+#define V2M_PA_CS1 0x0c000000
+#define V2M_PA_CS2 0x14000000
+#define V2M_PA_CS3 0x18000000
+#define V2M_PA_CS7 0x1c000000
+
+#define V2M_PERIPH_OFFSET(x) (x << 16)
+#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
+#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
+#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
+
+#define V2M_BASE 0x80000000
+#define CONFIG_SYS_TEXT_BASE 0x80800000
+#endif
+
+/*
+ * Physical addresses, offset from V2M_PA_CS0-3
+ */
+#define V2M_NOR0 (V2M_PA_CS0)
+#define V2M_NOR1 (V2M_PA_CS1)
+#define V2M_SRAM (V2M_PA_CS2)
+#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
+#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
+#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
+
+/* Common peripherals relative to CS7. */
+#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
+#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
+#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
+#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
+
+#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
+#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
+#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
+#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
+
+#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
+
+#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
+#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
+
+#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
+#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
+
+#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
+
+#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
+#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
+
+/* System register offsets. */
+#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
+#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
+#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
+
+/*
+ * Configuration
+ */
+#define SYS_CFG_START (1 << 31)
+#define SYS_CFG_WRITE (1 << 30)
+#define SYS_CFG_OSC (1 << 20)
+#define SYS_CFG_VOLT (2 << 20)
+#define SYS_CFG_AMP (3 << 20)
+#define SYS_CFG_TEMP (4 << 20)
+#define SYS_CFG_RESET (5 << 20)
+#define SYS_CFG_SCC (6 << 20)
+#define SYS_CFG_MUXFPGA (7 << 20)
+#define SYS_CFG_SHUTDOWN (8 << 20)
+#define SYS_CFG_REBOOT (9 << 20)
+#define SYS_CFG_DVIMODE (11 << 20)
+#define SYS_CFG_POWER (12 << 20)
+#define SYS_CFG_SITE_MB (0 << 16)
+#define SYS_CFG_SITE_DB1 (1 << 16)
+#define SYS_CFG_SITE_DB2 (2 << 16)
+#define SYS_CFG_STACK(n) ((n) << 12)
+
+#define SYS_CFG_ERR (1 << 1)
+#define SYS_CFG_COMPLETE (1 << 0)