+commit e1893815b0999410d7a327589611c7b38e95299e
+Author: Wolfgang Denk <wd@denx.de>
+Date: Fri Oct 12 15:49:39 2007 +0200
+
+ GP3 SSA: enable RTC
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+
+commit 8002012041f1ff9f997a5727abe5015f70cd2e46
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Tue Oct 9 13:58:24 2007 +0200
+
+ [ads5121] EEPROM support added.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 2b2a587d6d3076387d22ac740f44044bf46e2cb8
+Author: Marian Balakowicz <m8@semihalf.com>
+Date: Fri Oct 5 10:40:54 2007 +0200
+
+ tqm5200: Fix CONFIG_CMD_PCI typo in board config file.
+
+ Signed-off-by: Marian Balakowicz <m8@semihalf.com>
+
+commit 92869195ef8210758d2176230c0a36897afd50ed
+Author: Bartlomiej Sieka <tur@semihalf.com>
+Date: Fri Oct 5 09:46:06 2007 +0200
+
+ CM5200: Fix missing null-termination in hostname manipulation code
+
+ Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
+
+commit 738815c0cc44aa329097f868dc1efc49ede9c5ba
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:46 2007 +0200
+
+ ppc4xx: Coding style cleanup
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 87c1833a39e944db66385286fd5e28f9b3fcdd50
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Oct 2 11:44:19 2007 +0200
+
+ ppc4xx: lwmon5: Remove watchdog for now, since not fully tested yet
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 2db64784061bfc34f4ba70ef1d2fbe7133b55670
+Author: Grzegorz Bernacki <gjb@semihalf.com>
+Date: Mon Oct 1 09:51:50 2007 +0200
+
+ Program EPLD to force full duplex mode for PHY.
+
+ EPLD forces modes of PHY operation. By default full duplex is turned off.
+ This fix turns it on.
+
+ Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
+
+commit 86ec86c04326c3913178a7679aa910de071da75d
+Author: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+Date: Thu Sep 27 23:27:47 2007 +0200
+
+ Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serial
+
+ Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+
+commit 3e954beb614b5b190d7f4f4c3b641437a0132e35
+Author: Stefan Roese <sr@denx.de>
+Date: Tue Sep 11 14:12:55 2007 +0200
+
+ ppc4xx: lwmon5: Change GPIO 58 to default to low (watchdog test)
+
+ Signed-off-by: Stefan Roese <sr@denx.de>
+
+commit 0d38effc6e359e6b1b0c78d66e8bc1a4dc15a2ae
+Author: Grant Likely <grant.likely@secretlab.ca>
+Date: Tue Sep 25 15:48:05 2007 -0600
+
+ Fpga: fix incorrect test of CFG_FPGA_XILINX macro
+
+ CFG_FPGA_XILINX is a bit value used to test against the value in
+ CONFIG_FPGA. Testing for a value will always return TRUE. I don't
+ think that is the intention in this code.
+
+ Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
+
+commit 66dcad3a9a53e0766d90e0084123bd8529522fb0
+Author: Wolfgang Denk <wd@denx.de>
+Date: Thu Sep 20 00:04:14 2007 +0200
+
+ v1.3.0-rc2
+
+ Signed-off-by: Wolfgang Denk <wd@denx.de>
+