]> git.sur5r.net Git - u-boot/commitdiff
mpc85xx/t104xrdb: convert deep sleep to generic board interface
authorTang Yuantian <Yuantian.Tang@freescale.com>
Fri, 21 Nov 2014 03:17:16 +0000 (11:17 +0800)
committerYork Sun <yorksun@freescale.com>
Mon, 15 Dec 2014 17:17:12 +0000 (09:17 -0800)
A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
board/freescale/t104xrdb/ddr.c
board/freescale/t104xrdb/spl.c
board/freescale/t104xrdb/t104xrdb.c
include/configs/T104xRDB.h

index 2c331eebf9e60710b0dddd6bf58dd0a9df2190bb..5aa11b12a46ec44619b6a0598a6929b9e6b9b29a 100644 (file)
@@ -11,6 +11,7 @@
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr_dimm_params.h>
 #include <asm/fsl_law.h>
+#include <asm/mpc85xx_gpio.h>
 #include "ddr.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -109,6 +110,19 @@ found:
        popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
 }
 
+#if defined(CONFIG_DEEP_SLEEP)
+void board_mem_sleep_setup(void)
+{
+       void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
+
+       /* does not provide HW signals for power management */
+       clrbits_8(cpld_base + 0x17, 0x40);
+       /* Disable MCKE isolation */
+       gpio_set_value(2, 0);
+       udelay(1);
+}
+#endif
+
 phys_size_t initdram(int board_type)
 {
        phys_size_t dram_size;
@@ -124,5 +138,10 @@ phys_size_t initdram(int board_type)
 #else
        dram_size =  fsl_ddr_sdram_size();
 #endif
+
+#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
+       fsl_dp_resume();
+#endif
+
        return dram_size;
 }
index e394b121d281cb8e153cdbcba982c65c075274ca..4e8735b9ff19fb0112f799be3452657f54bf128b 100644 (file)
@@ -11,7 +11,7 @@
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <spi_flash.h>
-#include <asm/mpc85xx_gpio.h>
+#include "../common/sleep.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -64,8 +64,8 @@ void board_init_f(ulong bootflag)
 
 #ifdef CONFIG_DEEP_SLEEP
        /* disable the console if boot from deep sleep */
-       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+       if (is_warm_boot())
+               fsl_dp_disable_console();
 #endif
        /* compiler optimization barrier needed for GCC >= 3.4 */
        __asm__ __volatile__("" : : : "memory");
@@ -132,16 +132,3 @@ void board_init_r(gd_t *gd, ulong dest_addr)
        nand_boot();
 #endif
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-       void __iomem *cpld_base = (void *)CONFIG_SYS_CPLD_BASE;
-
-       /* does not provide HW signals for power management */
-       clrbits_8(cpld_base + 0x17, 0x40);
-       /* Disable MCKE isolation */
-       gpio_set_value(2, 0);
-       udelay(1);
-}
-#endif
index 4734f9dd93b17faf924661fc1a16efcd82214461..9cd5e157c483bac3d00673f2931c22b4b76a0de3 100644 (file)
@@ -17,8 +17,7 @@
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
 #include <fm_eth.h>
-#include <asm/mpc85xx_gpio.h>
-
+#include "../common/sleep.h"
 #include "t104xrdb.h"
 #include "cpld.h"
 
@@ -44,6 +43,16 @@ int checkboard(void)
        return 0;
 }
 
+int board_early_init_f(void)
+{
+#if defined(CONFIG_DEEP_SLEEP)
+       if (is_warm_boot())
+               fsl_dp_disable_console();
+#endif
+
+       return 0;
+}
+
 int board_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FLASH_BASE
@@ -113,14 +122,3 @@ int ft_board_setup(void *blob, bd_t *bd)
 
        return 0;
 }
-
-#ifdef CONFIG_DEEP_SLEEP
-void board_mem_sleep_setup(void)
-{
-       /* does not provide HW signals for power management */
-       CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
-       /* Disable MCKE isolation */
-       gpio_set_value(2, 0);
-       udelay(1);
-}
-#endif
index a54e0ebca27fce4fe8624283013d10d58acfb2d7..57cdf7213c4c6b3fa4233f36e02eb9ac50ebef23 100644 (file)
 
 /* support deep sleep */
 #define CONFIG_DEEP_SLEEP
+#if defined(CONFIG_DEEP_SLEEP)
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_SILENT_CONSOLE
+#endif
 
 #ifndef CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_TEXT_BASE   0xeff40000