u32 lpddr2io;
        struct control_lpddr2io_regs *lpddr2io_regs =
                (struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;
-       struct omap4_sys_ctrl_regs *const ctrl =
-               (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+       struct omap_sys_ctrl_regs *const ctrl =
+               (struct omap_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
 
        u32 omap4_rev = omap_revision();
 
 
 void do_io_settings(void)
 {
        u32 io_settings = 0, mask = 0;
-       struct omap5_sys_ctrl_regs *ioregs_base =
-                       (struct omap5_sys_ctrl_regs *) OMAP5_IOREGS_BASE;
+       struct omap_sys_ctrl_regs *ioregs_base =
+                     (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 
        /* Impedance settings EMMC, C2C 1,2, hsi2 */
        mask = (ds_mask << 2) | (ds_mask << 8) |
 
        unsigned int s32k_cr;   /* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
+struct omap_sys_ctrl_regs {
        unsigned int pad1[129];
        unsigned int control_id_code;                   /* 0x4A002204 */
        unsigned int pad11[22];
        unsigned int control_std_fuse_opp_bgap;         /* 0x4a002260 */
-       unsigned int pad2[47];
+       unsigned int pad2[24];                          /* 0x4a002264 */
+       unsigned int control_status;                    /* 0x4a0022c4 */
+       unsigned int pad3[22];                          /* 0x4a0022c8 */
        unsigned int control_ldosram_iva_voltage_ctrl;  /* 0x4A002320 */
        unsigned int control_ldosram_mpu_voltage_ctrl;  /* 0x4A002324 */
        unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
-       unsigned int pad3[260277];
+       unsigned int pad4[260277];
        unsigned int control_pbiaslite;                 /* 0x4A100600 */
-       unsigned int pad4[63];
+       unsigned int pad5[63];
        unsigned int control_efuse_1;                   /* 0x4A100700 */
        unsigned int control_efuse_2;                   /* 0x4A100704 */
 };
 
        unsigned int s32k_cr;   /* 0x10 */
 };
 
-#define OMAP5_IOREGS_BASE      0x4A002DA0
-
-struct omap5_sys_ctrl_regs {
+struct omap_sys_ctrl_regs {
+       u32 pad0[77]; /* 0x4A002000 */
+       u32 control_status; /* 0x4A002134 */
+       u32 pad1[794]; /* 0x4A002138 */
        u32 control_paconf_global; /* 0x4A002DA0 */
        u32 control_paconf_mode;  /* 0x4A002DA4 */
        u32 control_smart1io_padconf_0; /* 0x4A002DA8 */
        u32 control_smart2io_padconf_2; /* 0x4A002DBC */
        u32 control_smart3io_padconf_0; /* 0x4A002DC0 */
        u32 control_smart3io_padconf_1; /* 0x4A002DC4 */
-       u32 pad1[14];
+       u32 pad2[14];
        u32 control_pbias; /* 0x4A002E00 */
        u32 control_i2c_0; /* 0x4A002E04 */
        u32 control_camera_rx; /* 0x4A002E08 */
        u32 control_usb2phycore; /* 0x4A002E1C */
        u32 control_hdmi_1; /*0x4A002E20*/
        u32 control_hsi; /*0x4A002E24*/
-       u32 pad2[2];
+       u32 pad3[2];
        u32 control_ddr3ch1_0; /*0x4A002E30*/
        u32 control_ddr3ch2_0; /*0x4A002E34*/
        u32 control_ddrch1_0;   /*0x4A002E38*/
        u32 control_srcomp_east_side; /*0x4A002E7C*/
        u32 control_srcomp_west_side; /*0x4A002E80*/
        u32 control_srcomp_code_latch; /*0x4A002E84*/
-       u32 pad3[3680198];
+       u32 pad4[3680198];
        u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */
        u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */
        u32 control_padconf_mode; /* 0x4AE0CDA8 */
 
 static void omap4_vmmc_pbias_config(struct mmc *mmc)
 {
        u32 value = 0;
-       struct omap4_sys_ctrl_regs *const ctrl =
-               (struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;
+       struct omap_sys_ctrl_regs *const ctrl =
+               (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
 
 
        value = readl(&ctrl->control_pbiaslite);