#define TCFG_RESET BIT(0) /* software reset */
#define TCFG_EMUFREE BIT(1) /* behaviour of tmr on debug */
#define TCFG_IDLEMOD_SHIFT (2) /* power management */
-/* device type */
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
-#define TST_DEVICE 0x0
-#define EMU_DEVICE 0x1
-#define HS_DEVICE 0x2
-#define GP_DEVICE 0x3
/* cpu-id for AM43XX AM33XX and TI81XX family */
#define AM437X 0xB98C
unsigned char boot_device;
unsigned char reset_reason;
};
+
+#define DEVICE_TYPE_SHIFT 0x8
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
#endif
#endif
unsigned int s32k_cr; /* 0x10 */
};
+#define DEVICE_TYPE_SHIFT 0x8
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+
#endif /* __ASSEMBLY__ */
#ifndef __ASSEMBLY__
#define DEVICE_TYPE_SHIFT (0x8)
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
-#define DEVICE_GP 0x3
#endif /* __ASSEMBLY__ */
#define DEVICE_TYPE_SHIFT 0x6
#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
-#define DEVICE_GP 0x3
/* Output impedance control */
#define ds_120_ohm 0x0
u32 ctrl_core_sma_sw_1;
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
struct dpll_params {
u32 m;
u32 n;
u32 cm_div_h23_dpll;
u32 cm_div_h24_dpll;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
struct dplls {
const struct dpll_params *mpu;
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
enum {
OPP_LOW,
OPP_NOM,
struct volts eve;
struct volts iva;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const am33xx_ctrl;
+extern struct omap_sys_ctrl_regs const omap3_ctrl;
extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void scale_vcores(struct vcores_data const *);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
*/
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
#define EMU_DEVICE 0x1
#define HS_DEVICE 0x2
endif
obj-y += utils.o
+obj-y += sysinfo-common.o
ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),)
obj-y += hwinit-common.o
obj-y += clocks-common.o
obj-$(CONFIG_TI816X) += ti816x_emif4.o
obj-y += board.o
obj-y += mux.o
+obj-y += prcm-regs.o
+obj-y += hw_data.o
obj-$(CONFIG_CLOCK_SYNTHESIZER) += clk_synthesizer.o
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <asm/omap_common.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ hw_data_init();
early_system_init();
board_early_init_f();
sdram_init();
int arch_cpu_init_dm(void)
{
+ hw_data_init();
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
early_system_init();
#endif
--- /dev/null
+/*
+ * HW data initialization for AM33xx.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+void hw_data_init(void)
+{
+ *ctrl = &am33xx_ctrl;
+}
--- /dev/null
+/*
+ * HW regs data for AM33xx.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/hardware.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const am33xx_ctrl = {
+ .control_status = CTRL_BASE + 0x40,
+};
return partnum;
}
-/**
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- int mode;
- mode = readl(&cstat->statusreg) & (DEVICE_MASK);
- return mode >>= 8;
-}
-
/**
* get_sysboot_value(void) - return SYS_BOOT[4:0]
*/
return 0;
}
-/*
- * get_device_type(): tell if GP/HS/EMU/TST
- */
-u32 get_device_type(void)
-{
- return (readl((*ctrl)->control_status) &
- (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT;
-}
-
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
* Print CPU information
obj-y += boot.o
obj-y += clock.o
obj-y += sys_info.o
+obj-y += prcm-regs.o
+obj-y += hw_data.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
endif
return;
}
+void early_system_init(void)
+{
+ hw_data_init();
+}
+
/******************************************************************************
* Routine: s_init
* Description: Does early system init of muxing and clocks.
void s_init(void)
{
watchdog_init();
+ early_system_init();
try_unlock_memory();
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
+ early_system_init();
mem_init();
}
#endif
--- /dev/null
+/*
+ * HW data initialization for OMAP3.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const **ctrl =
+ (struct omap_sys_ctrl_regs const **)OMAP_SRAM_SCRATCH_SYS_CTRL;
+
+void hw_data_init(void)
+{
+ *ctrl = &omap3_ctrl;
+}
--- /dev/null
+/*
+ * HW regs data for OMAP3.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/omap_common.h>
+
+struct omap_sys_ctrl_regs const omap3_ctrl = {
+ .control_status = OMAP34XX_CTRL_BASE + 0x2F0,
+};
#include <asm/arch/mem.h> /* get mem tables */
#include <asm/arch/sys_proto.h>
#include <asm/bootm.h>
+#include <asm/omap_common.h>
#include <i2c.h>
#include <linux/compiler.h>
return (readl(&ctrl_base->status) & SYSBOOT_MASK);
}
-/*************************************************************
- * get_device_type(): tell if GP/HS/EMU/TST
- *************************************************************/
-u32 get_device_type(void)
-{
- return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
-}
-
#ifdef CONFIG_DISPLAY_CPUINFO
/**
* Print CPU information
--- /dev/null
+/*
+ * System information routines for all OMAP based boards.
+ *
+ * (C) Copyright 2017 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <asm/arch/omap.h>
+#include <asm/io.h>
+#include <asm/omap_common.h>
+
+/**
+ * Tell if device is GP/HS/EMU/TST.
+ */
+u32 get_device_type(void)
+{
+ return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >>
+ DEVICE_TYPE_SHIFT;
+}
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
+#include <asm/omap_common.h>
#include <asm/omap_sec_common.h>
#include <asm/omap_mmc.h>
#include <i2c.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/gpio.h>
#include <asm/emif.h>
+#include <asm/omap_common.h>
#include "../common/board_detect.h"
#include "board.h"
#include <power/pmic.h>
projects / u-boot / commitdiff