Driver/DDR: Update DDR driver to allow non-zero base address

The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.

Signed-off-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index b4988e194cfad3f20fcddabbc2dfb875181441b9..d0cd58925c368d09873222a5490b26937f24f772 100644 (file)
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -255,7 +255,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
                debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
        }
 
-       current_mem_base = 0ull;
+       current_mem_base = CONFIG_SYS_DDR_SDRAM_BASE;
        total_mem = 0;
        if (pinfo->memctl_opts[0].memctl_interleaving) {
                rank_density = pinfo->dimm_params[0][0].rank_density >>
@@ -535,8 +535,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
                        }
                }
 
-               total_mem = 1 + (((unsigned long long)max_end << 24ULL)
-                                   | 0xFFFFFFULL);
+               total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
+                           0xFFFFFFULL) - CONFIG_SYS_DDR_SDRAM_BASE;
        }
 
        return total_mem;