powerpc: Retain compatible property for L2 cache

When setting the compatible property for the L2 cache ensure that we
follow the documented binding by setting both
"<chip>-l2-cache-controller" and "cache" as values.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 12001f85e9fda6e324deb7902b68c682faf08f45..67140ba9ee181a1f102c5887153f0beafb809d16 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -180,6 +180,39 @@ static inline void ft_fixup_l3cache(void *blob, int off)
 #define ft_fixup_l3cache(x, y)
 #endif
 
+#if defined(CONFIG_L2_CACHE) || \
+       defined(CONFIG_BACKSIDE_L2_CACHE) || \
+       defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
+static inline void ft_fixup_l2cache_compatible(void *blob, int off)
+{
+       int len;
+       struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+
+       if (cpu) {
+               char buf[40];
+
+               if (isdigit(cpu->name[0])) {
+                       /* MPCxxxx, where xxxx == 4-digit number */
+                       len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
+                               cpu->name) + 1;
+               } else {
+                       /* Pxxxx or Txxxx, where xxxx == 4-digit number */
+                       len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
+                       tolower(cpu->name[0]), cpu->name + 1) + 1;
+               }
+
+               /*
+                * append "cache" after the NULL character that the previous
+                * sprintf wrote.  This is how a device tree stores multiple
+                * strings in a property.
+                */
+               len += sprintf(buf + len, "cache") + 1;
+
+               fdt_setprop(blob, off, "compatible", buf, len);
+       }
+}
+#endif
+
 #if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
@@ -215,9 +248,8 @@ static inline u32 l2cache_size(void)
 
 static inline void ft_fixup_l2cache(void *blob)
 {
-       int len, off;
+       int off;
        u32 *ph;
-       struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 
        const u32 line_size = 32;
        const u32 num_ways = 8;
@@ -243,28 +275,7 @@ static inline void ft_fixup_l2cache(void *blob)
                return ;
        }
 
-       if (cpu) {
-               char buf[40];
-
-               if (isdigit(cpu->name[0])) {
-                       /* MPCxxxx, where xxxx == 4-digit number */
-                       len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
-                               cpu->name) + 1;
-               } else {
-                       /* Pxxxx or Txxxx, where xxxx == 4-digit number */
-                       len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
-                               tolower(cpu->name[0]), cpu->name + 1) + 1;
-               }
-
-               /*
-                * append "cache" after the NULL character that the previous
-                * sprintf wrote.  This is how a device tree stores multiple
-                * strings in a property.
-                */
-               len += sprintf(buf + len, "cache") + 1;
-
-               fdt_setprop(blob, off, "compatible", buf, len);
-       }
+       ft_fixup_l2cache_compatible(blob, off);
        fdt_setprop(blob, off, "cache-unified", NULL, 0);
        fdt_setprop_cell(blob, off, "cache-block-size", line_size);
        fdt_setprop_cell(blob, off, "cache-size", size);
@@ -337,7 +348,7 @@ static inline void ft_fixup_l2cache(void *blob)
                        fdt_setprop_cell(blob, l2_off, "cache-size", size);
                        fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
                        fdt_setprop_cell(blob, l2_off, "cache-level", 2);
-                       fdt_setprop(blob, l2_off, "compatible", "cache", 6);
+                       ft_fixup_l2cache_compatible(blob, l2_off);
                }
 
                if (l3_off < 0) {