]> git.sur5r.net Git - u-boot/commitdiff
arm: mvebu: correct comments around cas_wl/cas_l
authorChris Packham <judge.packham@gmail.com>
Tue, 28 Nov 2017 21:38:34 +0000 (10:38 +1300)
committerStefan Roese <sr@denx.de>
Thu, 30 Nov 2017 07:30:59 +0000 (08:30 +0100)
The order of members in struct hws_topology_map is cas_wl, cas_l. The
comments in the original db-88f6820-gp.c had this wrong and have been
copied to other Armada-385 based boards. Practically this hasn't made a
difference since all these boards set both cas_wl and cas_l to 0
(autodetect) but if there were ever a board that did need to set these
explicitly they would run into unexpected issued.

Update the comments to reflect the correct order of structure members.

Reported-by: Tobi Wulff <tobi.wulff@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
board/CZ.NIC/turris_omnia/turris_omnia.c
board/Marvell/db-88f6820-amc/db-88f6820-amc.c
board/Marvell/db-88f6820-gp/db-88f6820-gp.c
board/gdsys/a38x/controlcenterdc.c
board/solidrun/clearfog/clearfog.c

index af66837909defadcd00210b61fdde698cdc59802..b03c0a3714b19833a0a486a94c3929443a647978 100644 (file)
@@ -212,7 +212,7 @@ static struct hws_topology_map board_topology_map_1g = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_NORMAL,            /* temperature */
            HWS_TIM_2T} },              /* timing (force 2t) */
        5,                              /* Num Of Bus Per Interface*/
@@ -231,7 +231,7 @@ static struct hws_topology_map board_topology_map_2g = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_8G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_NORMAL,            /* temperature */
            HWS_TIM_2T} },              /* timing (force 2t) */
        5,                              /* Num Of Bus Per Interface*/
index ac58f9085266b7cad399e76b52a1cce15f0dbc40..7db0095f75ef05befaa3643428ed402da255ffa4 100644 (file)
@@ -68,7 +68,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_8,                /* memory_width */
            MEM_2G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index a1974cb4bd21138eaad9b9ce9dbe08cc3acfaa13..b95cd1d4aab5b99cb18c993fd6f54ff0761067d4 100644 (file)
@@ -89,7 +89,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_8,                /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index 32168d35768a1a6375c2497276b5ed7294239c81..3d74a6dfb89726cc80ee43cfe41c9e476cf47ecf 100644 (file)
@@ -52,7 +52,7 @@ static struct hws_topology_map ddr_topology_map = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_533,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/
index 8906636f7646d931ee6051b28a58f0a13567d50e..1472e9793e5f3619e3802b1d5264e250baa5add2 100644 (file)
@@ -82,7 +82,7 @@ static struct hws_topology_map board_topology_map = {
            BUS_WIDTH_16,               /* memory_width */
            MEM_4G,                     /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
+           0, 0,                       /* cas_wl cas_l */
            HWS_TEMP_LOW,               /* temperature */
            HWS_TIM_DEFAULT} },         /* timing */
        5,                              /* Num Of Bus Per Interface*/