return 0;
err1:
- dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
+ dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
err0:
if (!dwc->nr_scratch)
return;
- dma_unmap_single((void *)dwc->scratch_addr, dwc->nr_scratch *
+ dma_unmap_single((void *)(uintptr_t)dwc->scratch_addr, dwc->nr_scratch *
DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
kfree(dwc->scratchbuf);
}
dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
dwc->mem = mem;
- dwc->regs = (int *)(dwc3_dev->base + DWC3_GLOBALS_REGS_START);
+ dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
+ DWC3_GLOBALS_REGS_START);
/* default to highest possible threshold */
lpm_nyet_threshold = 0xff;
trb->ctrl |= (DWC3_TRB_CTRL_IOC
| DWC3_TRB_CTRL_LST);
- dwc3_flush_cache((int)buf_dma, len);
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)buf_dma, len);
+ dwc3_flush_cache((long)trb, sizeof(*trb));
if (chain)
return 0;
if (!r)
return;
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
status = DWC3_TRB_SIZE_TRBSTS(trb->size);
if (status == DWC3_TRBSTS_SETUP_PENDING) {
ur->actual += transferred;
trb++;
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
length = trb->size & DWC3_TRB_SIZE_MASK;
ep0->free_slot = 0;
maxp);
transferred = min_t(u32, ur->length - transferred,
transfer_size - length);
- dwc3_flush_cache((int)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
+ dwc3_flush_cache((long)dwc->ep0_bounce, DWC3_EP0_BOUNCE_SIZE);
memcpy(buf, dwc->ep0_bounce, transferred);
} else {
transferred = ur->length - length;
list_del(&req->list);
req->trb = NULL;
- dwc3_flush_cache((int)req->request.dma, req->request.length);
+ dwc3_flush_cache((long)req->request.dma, req->request.length);
if (req->request.status == -EINPROGRESS)
req->request.status = status;
trb->ctrl |= DWC3_TRB_CTRL_HWO;
- dwc3_flush_cache((int)dma, length);
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)dma, length);
+ dwc3_flush_cache((long)trb, sizeof(*trb));
}
/*
slot %= DWC3_TRB_NUM;
trb = &dep->trb_pool[slot];
- dwc3_flush_cache((int)trb, sizeof(*trb));
+ dwc3_flush_cache((long)trb, sizeof(*trb));
__dwc3_cleanup_done_trbs(dwc, dep, req, trb, event, status);
dwc3_gadget_giveback(dep, req, status);
for (i = 0; i < dwc->num_event_buffers; i++) {
evt = dwc->ev_buffs[i];
- dwc3_flush_cache((int)evt->buf, evt->length);
+ dwc3_flush_cache((long)evt->buf, evt->length);
}
dwc3_thread_interrupt(0, dwc);
#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
static inline u32 dwc3_readl(void __iomem *base, u32 offset)
{
- u32 offs = offset - DWC3_GLOBALS_REGS_START;
+ unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
u32 value;
/*
static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
{
- u32 offs = offset - DWC3_GLOBALS_REGS_START;
+ unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
/*
* We requested the mem region starting from the Globals address