]> git.sur5r.net Git - u-boot/commitdiff
ppc4xx: Small whitespace fix of esd patches
authorStefan Roese <sr@denx.de>
Mon, 31 Mar 2008 10:20:48 +0000 (12:20 +0200)
committerStefan Roese <sr@denx.de>
Mon, 31 Mar 2008 10:20:48 +0000 (12:20 +0200)
Signed-off-by: Stefan Roese <sr@denx.de>
board/esd/pmc440/cmd_pmc440.c
board/esd/pmc440/pmc440.c
include/configs/DU440.h

index e9e9746b8127dea3bc22c1ea7f5215680ca4d770..90d93095558f7b201f2557cd2fe4d3840b6c465b 100644 (file)
@@ -503,15 +503,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
                /* map PCI address at 0xc0000000 in PLB space */
 
-                /* PMM1 Mask/Attribute - disabled b4 setting */
+               /* PMM1 Mask/Attribute - disabled b4 setting */
                out32r(PCIX0_PMM1MA, 0x00000000);
-                /* PMM1 Local Address */
+               /* PMM1 Local Address */
                out32r(PCIX0_PMM1LA, 0xc0000000);
-                /* PMM1 PCI Low Address */
+               /* PMM1 PCI Low Address */
                out32r(PCIX0_PMM1PCILA, pciaddr);
-                /* PMM1 PCI High Address */
+               /* PMM1 PCI High Address */
                out32r(PCIX0_PMM1PCIHA, 0x00000000);
-                /* 256MB + No prefetching, and enable region */
+               /* 256MB + No prefetching, and enable region */
                out32r(PCIX0_PMM1MA, 0xf0000001);
        } else {
                printf("Usage:\npmm %s\n", cmdtp->help);
index 7fadc42bc245fd845de41cf2e85aaf32d574a8bf..5b811bba9adcea4f8f51776bf3f695844e2452d8 100644 (file)
@@ -565,7 +565,7 @@ void pci_target_init(struct pci_controller *hose)
        pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
                              CFG_PCI_SUBSYS_VENDORID);
 
-        /* disabled for PMC405 backward compatibility */
+       /* disabled for PMC405 backward compatibility */
        /* Configure command register as bus master */
        /* pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); */
 
index f193a431d78167def6aeec39dce80b908df9bf9f..d54da9717b7326193655286a2d09863278f26e4a 100644 (file)
 #define CFG_MBYTES_SDRAM        (1024) /* 512 MiB      TODO: remove    */
 #define CONFIG_DDR_DATA_EYE            /* use DDR2 optimization        */
 #define CFG_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
-                                        /* 440EPx errata CHIP 11        */
+                                       /* 440EPx errata CHIP 11        */
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for setup     */
 #define CONFIG_DDR_ECC                 /* Use ECC when available       */
 #define SPD_EEPROM_ADDRESS     {0x50}