]> git.sur5r.net Git - u-boot/commitdiff
Some 85xx cpu cleanups
authorAndy Fleming <afleming@freescale.com>
Mon, 23 Apr 2007 06:44:44 +0000 (01:44 -0500)
committerAndrew Fleming-AFLEMING <afleming@freescale.com>
Tue, 24 Apr 2007 00:58:28 +0000 (19:58 -0500)
* Cleaned up the TSR[WIS] clearing
* Cleaned up DMA initialization

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
cpu/mpc85xx/cpu.c

index 2fe6bdf4b942f8e38bf3485ed0fbe5765ebbf304..b701b477b162c443abfa1b0a2d282bdce08bdaf2 100644 (file)
@@ -198,9 +198,9 @@ reset_85xx_watchdog(void)
         * Clear TSR(WIS) bit by writing 1
         */
        unsigned long val;
-       val = mfspr(tsr);
-       val |= 0x40000000;
-       mtspr(tsr, val);
+       val = mfspr(SPRN_TSR);
+       val |= TSR_WIS;
+       mtspr(SPRN_TSR, val);
 }
 #endif /* CONFIG_WATCHDOG */
 
@@ -211,6 +211,7 @@ void dma_init(void) {
 
        dma->satr0 = 0x02c40000;
        dma->datr0 = 0x02c40000;
+       dma->sr0 = 0xfffffff; /* clear any errors */
        asm("sync; isync; msync");
        return;
 }
@@ -225,6 +226,10 @@ uint dma_check(void) {
                status = dma->sr0;
        }
 
+       /* clear MR0[CS] channel start bit */
+       dma->mr0 &= 0x00000001;
+       asm("sync;isync;msync");
+
        if (status != 0) {
                printf ("DMA Error: status = %x\n", status);
        }