#define CFG_PEHLPAR            0xC0
 #define CFG_PUAPAR             0x0F            /* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA              0x05
-#define CFG_PJPAR              0xFF;
+#define CFG_PJPAR              0xFF
 
 /*-----------------------------------------------------------------------
  * CCM configuration
 
  * You should know what you are doing if you make changes here.
  */
 #define CFG_MBAR               0x10000000      /* Register Base Addrs */
-#define CFG_SCR                        0x0003;
-#define CFG_SPR                        0xffff;
+#define CFG_SCR                        0x0003
+#define CFG_SPR                        0xffff
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
 
 #define CFG_PEHLPAR            0xC0
 #define CFG_PUAPAR             0x0F    /* UA0..UA3 = Uart 0 +1 */
 #define CFG_DDRUA              0x05
-#define CFG_PJPAR              0xFF;
+#define CFG_PJPAR              0xFF
 
 #endif                         /* _CONFIG_M5282EVB_H */
 
                                | SDRAM_CFG_32_BE )
                                /* 0x43080000 */
 #endif
-#define CFG_SDRAM_CFG2         0x00401000;
+#define CFG_SDRAM_CFG2         0x00401000
 /* set burst length to 8 for 32-bit data path */
 #define CFG_DDR_MODE           ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
                                | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
                                /* 0x44480632 */
-#define CFG_DDR_MODE_2         0x8000C000;
+#define CFG_DDR_MODE_2         0x8000C000
 
 #define CFG_DDR_CLK_CNTL       DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
                                /*0x02000000*/
 
 #define CFG_DDR_MODE           ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
                                | (0x0442 << SDRAM_MODE_SD_SHIFT))
                                /* 0x04400442 */ /* DDR400 */
-#define CFG_DDR_MODE2          0x00000000;
+#define CFG_DDR_MODE2          0x00000000
 
 /*
  * Memory test
 
  * ---
  */
 
-#define CFG_SCR                        0x0003;
-#define CFG_SPR                        0xffff;
+#define CFG_SCR                        0x0003
+#define CFG_SPR                        0xffff
 
 /* ---
  * Ethernet settings
 
 #define CFG_BR3 ((CFG_SPC1920_HPI_BASE & BR_BA_MSK) | \
                                               BR_MS_UPMA | \
                                               BR_PS_16 | \
-                                              BR_V);
+                                              BR_V)
 
 #define CFG_MAMR (MAMR_GPL_A4DIS | \
                MAMR_RLFA_5X | \
                                        OR_SCY_4_CLK | \
                                        OR_TRLX)
 
-#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR4 ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * PLD CS5
                                        OR_SCY_0_CLK | \
                                        OR_TRLX)
 
-#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
+#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 
 /*
  * Internal Definitions